METHODS AND DEVICES FOR SOLDERLESS INTEGRATION OF MULTIPLE SEMICONDUCTOR DIES ON FLEXIBLE SUBSTRATES

• US 20190311989A1
• Filed: 04/10/2019
• Published: 10/10/2019
• Est. Priority Date: 04/10/2018
• Status: Active Grant

• Current Assignee: WiSpry, Inc (AAC Technologies Holdings Inc.)
• Original Assignee: WiSpry, Inc (AAC Technologies Holdings Inc.)
• Inventors: Hadizadeh, Rameen
• Granted Patent: US 10,679,946 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 24/08 of an individual bonding area
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/351 Thermal stress

Abstract

Methods and devices for solderless integration of multiple semiconductor dies on flexible substrates. In some embodiments, a method for solderless integration of multiple semiconductor dies on flexible substrates includes arranging one or a plurality of semiconductor dies on a first carrier, active side down, and then depositing a sacrificial material over them. In some embodiments, the method further includes removing the first carrier and then building a wafer-level redistribution layer (RDL) over the active side of the one or plurality of semiconductor dies and the sacrificial material. In some embodiments, the method includes patterning the wafer-level RDL to form an outline of a final module footprint and then applying a second carrier to the wafer-level RDL. In some embodiments, the method can also include removing the sacrificial material from the one or plurality of semiconductor dies and the wafer-level RDL to achieve an integration of the one or plurality of semiconductor dies.

Claims

1. A method for packaging one or more semiconductor dies for use in flexible electronics, the method comprising:

arranging one or more semiconductor dies, each comprising at least an active side, in a desired arrangement within a sacrificial material layer;

building a wafer-level redistribution layer (RDL) over the active side of each of the one or more semiconductor dies and the sacrificial material layer, wherein the wafer-level RDL forms a directly metallized connection with the active side of each of the one or more semiconductor dies;

patterning a portion of the wafer-level RDL to form an outline of a final module footprint;

affixing a first carrier to the wafer-level RDL built over the active side of the one or more semiconductor dies and the sacrificial material layer;

removing at least a portion of the sacrificial material layer from the one or more semiconductor dies and the wafer-level RDL to achieve an integration of the one or more semiconductor dies; and

removing the first carrier from the active side of the one or more semiconductor dies or individually removing integrated semiconductor dies, along with their respective wafer-level RDLs, from the first carrier;

wherein the wafer-level RDL comprises a flexible substrate material and serves as a flexible supporting substrate of the one or more semiconductor dies.

2. The method of claim 1, wherein the one or more semiconductor dies comprises a plurality of semiconductor dies.

3. The method of claim 2, wherein the flexible substrate material comprises die-to-die interconnects with material properties that reduce stress caused by cyclic thermal expansion and contraction.

4. The method of claim 1, wherein the wafer-level RDL comprises one or more contacts;

and

wherein each of the one or more contacts is in electronic communication with at least one semiconductor die of the one or more semiconductor dies.

5. The method of claim 4, wherein the one or more contacts comprise a metal selected from the group consisting of copper, aluminum, nickel, gold, titanium, vanadium, silver, and chromium.

6. The method of claim 4, further comprising exposing the one or more contacts on an opposite side of the wafer-level RDL as the one or more semiconductor dies.

7. The method of claim 4, further comprising providing redistribution metals or dielectrics, or redistribution metals and dielectrics, without solder, as a structural and electrical connection between the one or more semiconductor dies and the one or more contacts.

8. The method of claim 1, wherein the one or more semiconductor dies are plasma-diced or non-rectangular in shape.

9. The method of claim 8, wherein the one or more semiconductor dies are arranged in close proximity to one another for bendable applications.

10. The method of claim 1, wherein arranging the one or more semiconductor dies in the desired arrangement comprises arranging the one or more semiconductor dies on a second carrier, wherein the active side of each of the one or more semiconductor dies is placed on the first carrier.

11. The method of claim 10, wherein the sacrificial material layer is deposited over the one or more semiconductor dies and the second carrier.

12. The method of claim 11 further comprising removing the second carrier from the sacrificial material layer and the one or more semiconductor dies.

13. An integrated circuit device comprising:

one or more semiconductor dies, each comprising at least an active side; and

a wafer-level redistribution layer (RDL) that forms a directly metallized connection with the active side of each of the one or more semiconductor dies and comprises a flexible substrate material that supports the one or more semiconductor dies together, while allowing substantial movement of the wafer-level RDL in any direction with respect to the one or more semiconductor dies and without any physically observable deformation in the integrated circuit device.

14. The integrated circuit device of claim 13, wherein the one or more semiconductor dies comprises a plurality of semiconductor dies.

15. The integrated circuit device of claim 14, wherein the flexible substrate material comprises die-to-die interconnects with material properties configured to reduce stress caused by cyclic thermal expansion and contraction;

and

wherein the one or more semiconductor dies is substantially less flexible than the wafer-level RDL.

16. The integrated circuit device of claim 13, wherein the wafer-level RDL comprises one or more contacts;

and

wherein each of the one or more contacts is in communication with at least one semiconductor die of the one or more semiconductor dies.

17. The integrated circuit device of claim 16, wherein the contacts comprise a metal selected from a group consisting of copper, aluminum, nickel, gold, titanium, vanadium, silver, and chromium.

18. The integrated circuit device of claim 13, wherein the one or more semiconductor dies are plasma-diced or non-rectangular in shape.

19. The integrated circuit device of claim 18, wherein the one or more semiconductor dies are arranged in close proximity to each other for bendable applications.

20. The integrated circuit device of claim 13, further comprising redistribution metals or dielectrics, or redistribution metals and dielectrics, without solder, as a structural and electrical connection between the one or more semiconductor dies and the one or more contacts.

21. An integrated circuit module for use in flexible electronics manufactured by a process comprising:

arranging one or more semiconductor dies, each comprising at least an active side, in a desired arrangement within a sacrificial material layer;

building a wafer-level redistribution layer (RDL) over the active side of each of the one or more semiconductor dies and the sacrificial material layer, wherein the wafer-level RDL forms a directly metallized connection with the active side of each of the one or more semiconductor dies;

patterning a portion of the wafer-level RDL to form an outline of a final module footprint;

affixing a first carrier to the wafer-level RDL built over the active side of the one or more semiconductor dies and the sacrificial material layer;

removing at least a portion or all of the sacrificial material layer from the one or more semiconductor dies and the wafer-level RDL to achieve an integration of the one or more semiconductor dies; and

removing the first carrier from the active side of the one or more semiconductor dies or individually removing integrated semiconductor dies, along with their respective wafer-level RDL, from the first carrier;

wherein the wafer-level RDL comprises a flexible substrate material that serves as a flexible supporting substrate of the one or more semiconductor dies; and

wherein the one or more semiconductor dies is significantly less flexible than the wafer-level RDL.

22. The integrated circuit module of claim 21, wherein the one or more semiconductor dies comprises a plurality of semiconductor dies.

23. The integrated circuit module of claim 22, wherein the flexible substrate material comprises die-to-die interconnects with material properties that reduce stress caused by cyclic thermal expansion and contraction.

24. The integrated circuit module of claim 21, wherein the wafer-level RDL comprises one or more contacts;

wherein each of the one or more contacts is in electronic communication with at least one semiconductor die of the one or more semiconductor dies.

25. The integrated circuit module of claim 24, wherein the contacts comprise a metal selected from a group consisting of copper, aluminum, nickel, gold, titanium, vanadium, silver, and chromium.

26. The integrated circuit module of claim 24, the process further comprising exposing the one or more contacts on an opposite side of the wafer-level RDL as the one or more semiconductor dies.

27. The integrated circuit module of claim 21, wherein the one or more semiconductor dies are plasma-diced or non-rectangular in shape.

28. The integrated circuit module of claim 27, wherein the one or more semiconductor dies are arranged in close proximity to each other for wearable applications.

29. The integrated circuit module of claim 21, the process further comprising providing redistribution metals or dielectrics, or redistribution metals and dielectrics, without solder, as a structural and electrical connection between the one or more semiconductor dies and the one or more contacts.

30. The integrated circuit module of claim 21, wherein arranging the one or more semiconductor dies in the desired arrangement comprises arranging the one or more semiconductor dies on a second carrier, wherein the active side of each of the one or more semiconductor dies is placed on the first carrier.

31. The integrated circuit module of claim 30 wherein the sacrificial material layer is deposited over the one or more semiconductor dies and the second carrier.

32. The integrated circuit module of claim 31 further comprising removing the second carrier from the sacrificial material layer and the one or more semiconductor dies.