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WARPING REDUCTION IN SILICON WAFERS

  • US 20190311995A1
  • Filed: 04/04/2018
  • Published: 10/10/2019
  • Est. Priority Date: 04/04/2018
  • Status: Active Grant
First Claim
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1. An integrated circuit wafer, comprising:

  • a silicon substrate that includes;

    a plurality of integrated circuit chips; and

    a plurality of scribe regions situated between ones of the plurality of integrated circuit chips, wherein a particular scribe region of the plurality of scribe regions has a total area and includes a plurality of layers, wherein the particular scribe region includes a stress reduction structure located on at least a particular layer of the plurality of layers, wherein the stress reduction structure includes, at the particular layer, a material, wherein a collective area of the material at the particular layer is at least 40 percent of the total area of the particular scribe region, and wherein the material has a coefficient of thermal expansion that is greater than a coefficient of thermal expansion of the silicon substrate.

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