METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND MOUNTING DEVICE

• US 20190312020A1
• Filed: 09/28/2017
• Published: 10/10/2019
• Est. Priority Date: 09/30/2016
• Status: Active Grant

• Current Assignee: Shinkawa Ltd. (Yamaha Corporation)
• Original Assignee: Shinkawa Ltd. (Yamaha Corporation)
• Inventors: NAKAMURA, Tomonori, MAEDA, Toru
• Granted Patent: US 10,896,901 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/75251 in the lower part of the bonding apparatus, e.g. in the apparatus chuck
• CPC Class Codes: H01L 2224/75252 in the upper part of the bonding apparatus, e.g. in the bonding head
• CPC Class Codes: H01L 2224/7555 Mechanical means, e.g. for planarising, pressing, stamping
• CPC Class Codes: H01L 2224/7565 Means for transporting the components to be connected
• CPC Class Codes: H01L 2224/75901 using a computer, e.g. fully- or semi-automatic bonding
• CPC Class Codes: H01L 2224/8113 using marks formed on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81132 using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81986 Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2224/8313 using marks formed on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83132 : using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
• CPC Class Codes: H01L 2224/83191 : wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/8385 : using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/83856 : Pre-cured adhesive, i.e. B-stage adhesive
• CPC Class Codes: H01L 2224/83986 : Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2224/92143 : the second connecting process involving a bump connector
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06565 : the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/065 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/07 : the devices being of a type provided for in group H01L29/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0635 : Acrylic polymer
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/0685 : Polyether
• CPC Class Codes: H01L 2924/07025 : Polyimide
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor

Abstract

The disclosure is provided with: a temporary crimping step in which one or more semiconductor chips 10 are sequentially laminated while being temporarily crimped in each of two or more locations on a substrate 30 to thereby form chip stacks ST in a temporarily crimped state; and a permanent crimping step in which the top surfaces of all of the chip stacks ST formed in the temporarily crimped state are sequentially heated, pressurized, and permanently crimped. Furthermore, a specifying step is provided prior to the temporary crimping step for specifying a separation distance Dd which is the distance from the chip stacks ST under permanent crimping to a location at which the temperature of the substrate 30, the temperature having been raised by heating for the permanent crimping, becomes less than or equal to a prescribed permissible temperature Td, and in the temporary crimping step, the chip stacks ST in the temporarily crimped state are formed separated from each other by the separation distance Dd or more.

Claims

1. A method of manufacturing a semiconductor device in which one or more semiconductor chips are laminated and mounted in a plurality of locations on a substrate, comprising:

a temporary crimping step of sequentially laminating the one or more semiconductor chips in each of two or more locations on the substrate while temporarily crimping the one or more semiconductor chips to thereby form chip stacks in a temporarily crimped state; and

a permanent crimping step of sequentially heating and pressurizing top surfaces of all of the chip stacks formed in the temporarily crimped state to thereby collectively permanently crimp the one or more semiconductor chips which form each of the chip stacks,

wherein the method

repeats the temporary crimping step and the permanent crimping step twice or more until a desired number of the chip stacks are reached,

further comprises a specifying step prior to the temporary crimping step for specifying a separation distance which is a distance from the chip stacks under permanent crimping to a location at which a temperature of the substrate, the temperature having been raised by heating for the permanent crimping, becomes less than or equal to a prescribed permissible temperature,

in the temporary crimping step, forms the chip stacks in the temporarily crimped state to be separated from each other by the separation distance or more, and

in the permanent crimping step, permanently crimps the chip stacks which are in the temporarily crimped state and are formed separated from each other by the separation distance or more.

2. The method of manufacturing a semiconductor device according to claim 1, wherein

the specifying step specifies the separation distance based on mounting conditions of the semiconductor chips.

3. The method of manufacturing a semiconductor device according to claim 2, wherein

a lower layer temperature which is a temperature of lowermost layers of the chip stacks when the permanent crimping step is performed is comprised,

in the specifying step, the separation distance is specified so that the separation distance becomes greater as the lower layer temperature is greater.

4. The method of manufacturing a semiconductor device according to claim 1, wherein

a thermosetting resin is provided on an end surface at one side of the semiconductor chip in a laminating direction for fixing the semiconductor chip to the substrate or to another semiconductor chip mounted adjacent to the one side in the laminating direction, and

the permissible temperature is less than a curing start temperature at which the thermosetting resin starts to cure irreversibly.

5. The method of manufacturing a semiconductor device according to claim 1, further comprising:

a map forming step of forming a map indicating formation positions of the plurality of chip stacks based on the specified separation distance,

wherein in the temporary crimping step, the plurality of chip stacks in the temporarily crimped state are formed according to the map.

6. The method of manufacturing a semiconductor device according to claim 1, wherein

a plurality of disposition regions in which the chip stacks are disposed further set to be arranged in a lattice shape at a prescribed pitch P on the substrate,

the specifying step, after specifying the separation distance and when setting the separation distance as Dd, further specifies an integer N satisfying {(N−

1)×

P}≤

Dd<

N×

P, and

in the temporary crimping step, the chip stacks in the temporarily crimped state are formed with N disposition regions therebetween.

7. The method of manufacturing a semiconductor device according to claim 1, wherein the substrate is a semiconductor wafer.

8. A method of manufacturing a semiconductor device, comprising:

a temporary crimping step of sequentially laminating one or more semiconductor chips in each of two or more locations on a substrate while temporarily crimping the one or more semiconductor chips to thereby form chip stacks in a temporarily crimped state; and

a permanent crimping step of repeating twice or more a process of simultaneously heating and pressurizing top surfaces of the two or more chip stacks in the temporarily crimped state and simultaneously performing permanent crimping to change all of the chip stacks in the temporarily crimped state formed in the temporary crimping step to a permanently crimped state,

wherein the method

repeats the temporary crimping step and the permanent crimping step twice or more until a desired number of the chip stacks are reached,

further comprises a specifying step prior to the temporary crimping step for specifying a separation distance which is a distance from the chip stacks under permanent crimping to a location at which a temperature of the substrate, the temperature having been raised by heating for the permanent crimping, becomes less than or equal to a prescribed permissible temperature, and

in the temporary crimping step, forms the chip stacks in the temporarily crimped state not to be permanently crimped simultaneously to be separated from each other by the separation distance or more.

9. A mounting device for laminating and mounting one or more semiconductor chips in a plurality of locations on a substrate, comprising:

a temporary crimping means of sequentially laminating the one or more semiconductor chips in each of two or more locations on the substrate while temporarily crimping the one or more semiconductor chips to thereby form chip stacks in a temporarily crimped state;

a permanent crimping means of sequentially heating and pressurizing top surfaces of all of the chip stacks formed in the temporarily crimped state to thereby collectively permanently crimp the one or more semiconductor chips which form each of the chip stacks; and

a separation distance specifying means for specifying a separation distance prior to the temporary crimping, the separation distance being a distance from the chip stacks under permanent crimping to a location at which a temperature of the substrate, the temperature having been raised by heating for the permanent crimping, becomes less than or equal to a prescribed permissible temperature,

wherein the temporary crimping means forms the chip stacks in the temporarily crimped state to be separated from each other by the separation distance or more, and

the permanent crimping means permanently crimps the chip stacks which are in the temporarily crimped state and are formed separated from each other by the separation distance or more.

10. A mounting device for laminating and mounting one or more semiconductor chips in a plurality of locations on a substrate, comprising:

a bonding part for sequentially laminating the one or more semiconductor chips in each of two or more locations on the substrate while temporarily crimping the one or more semiconductor chips to thereby form chip stacks in a temporarily crimped state and for sequentially heating and pressurizing top surfaces of all of the chip stacks formed in the temporarily crimped state to thereby collectively permanently crimp the one or more semiconductor chips which form each of the chip stacks;

a separation distance specifying means for specifying a separation distance prior to the temporary crimping, the separation distance being a distance from the chip stacks under permanent crimping to a location at which a temperature of the substrate, the temperature having been raised by heating for the permanent crimping, becomes less than or equal to a prescribed permissible temperature; and

a control part for controlling the bonding part so that after the chip stacks in the temporarily crimped state are formed separated from each other by the separation distance or more, the chip stacks formed in the temporarily crimped state are permanently crimped.