INTEGRATED CIRCUIT DEVICE WITH CRENELLATED METAL TRACE LAYOUT
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Abstract
Integrated circuit (IC) cell architectures including a crenellated interconnect trace layout. A crenellated trace layout may be employed where an IC cell includes transistor having a source/drain terminal interconnected through a back-side (3D) routing scheme that reduces front-side routing density for a given transistor footprint. In the crenellated layout, adjacent interconnect traces or tracks may have their ends staggered according to a crenellation phase for the cell. Crenellated tracks may intersect one cell boundary with adjacent tracks intersecting an opposite cell boundary. Track ends may be offset by at least the width of an underlying orthogonal interconnect trace. Crenellated track ends may be offset by the width of an underlying orthogonal interconnect trace and half a spacing between adjacent orthogonal interconnect traces.
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Citations
43 Claims
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1-23. -23. (canceled)
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24. The IC An integrated circuit (IC) structure, comprising:
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a trace layout include a plurality of traces extending in a direction, wherein individual ones of the plurality of traces intersect only one boundary of the structure; and adjacent ones of the plurality of traces are staggered to intersect boundaries on opposite sides of the structure. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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39. An integrated IC block, comprising:
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a first IC structure having a first trace layout including; a first plurality of traces extending in a direction, wherein individual ones of the traces intersect only one boundary of the first IC structure; and adjacent ones of the first plurality of traces are staggered to intersect boundaries on opposite sides of the first IC structure; and a second IC structure sharing one boundary with the first IC structure, wherein; the second IC structure has a second trace layout comprising a second plurality of traces extending in the direction, ones of the second traces intersecting only one boundary of the second IC structure, and having second ends that are laterally offset from each other in the direction by at least the width of an orthogonal trace in a second interconnect level; and wherein a trace of the first plurality intersecting the shared boundary is laterally offset in the direction from a trace of the second plurality by at least the width of an orthogonal trace in the second interconnect level. - View Dependent Claims (40, 41, 42)
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43. A method of fabricating an integrated circuit (IC) structure, the method comprising:
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forming a gate electrode extending in a first direction over a transistor channel semiconductor; forming a first interconnect level comprising at least a first interconnect trace adjacent to a second interconnect trace and extending in a second direction over the gate electrode, wherein the first and second interconnect traces have a first trace width and are separated from one another in the first direction by an interconnect trace spacing; forming a second interconnect level over the first interconnect level, the second interconnect level comprising a plurality of traces extending in the first direction, wherein; individual traces of the plurality intersect only one boundary of the structure; adjacent traces of the plurality are staggered in the first direction to intersect boundaries on opposite sides of the structure; and individual traces of the plurality have an end that is laterally offset from that of an adjacent trace by a distance in the first direction that is at least equal to the first interconnect trace width.
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Specification