ON-CHIP METAL-INSULATOR-METAL (MIM) CAPACITOR AND METHODS AND SYSTEMS FOR FORMING SAME

• US 20190312028A1
• Filed: 04/09/2018
• Published: 10/10/2019
• Est. Priority Date: 04/09/2018
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Park, Chanro, Xie, Ruilong, Cheng, Kangguo, Li, Juntao
• Granted Patent: US 10,770,454 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

We report a semiconductor device, containing a semiconductor substrate; an isolation feature on the substrate; a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and disposed on and in contact with at least one side of the gate electrode; and a fill metal between the plurality of gates on the isolation feature. We also report methods of forming such a device, and a system for manufacturing such a device.

Claims

1. A method, comprising:

forming an isolation feature on a semiconductor substrate;

forming a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and disposed on and in contact with at least one side of the gate electrode; and

depositing a fill metal between the plurality of gates on the isolation feature, wherein the fill metal after deposition is in contact with the high-k dielectric layer on at least one side of at least one of the plurality of gates.

2. The method of claim 1, wherein the fill metal is in contact with the high-k dielectric layer on the at least one side of the gate electrode.

3. The method of claim 1, wherein forming the isolation feature comprises forming the isolation feature in an inactive region.

4. The method of claim 1, further comprising:

forming a fin in an active region on the semiconductor substrate;

forming at least one gate on the fin, wherein the at least one gate comprises a gate electrode, a high-k dielectric layer disposed between the gate electrode and the fin and disposed on and in contact with at least one side of the gate electrode,

forming a spacer disposed on and in contact with the high-k dielectric layer on at least one side of the gate electrode of the at least one gate on the fin and disposed on and in contact with the high-k dielectric layer on at least one side of each gate electrode of the plurality of gates on the isolation feature;

forming at least two sources/drains (S/Ds), each S/D disposed on and/or in the fin adjacent to the spacer on each side of the at least one gate;

forming an interlayer dielectric (ILD) over each S/D and between the plurality of gates on the isolation feature, wherein the ILD is disposed in contact with the spacer;

removing the ILD over each S/D and between the plurality of gates on the isolation feature, to yield a plurality of contact trenches each exposing either one of the S/Ds or the isolation feature;

masking the at least one gate and the at least two S/Ds on the fin;

removing the plurality of spacers disposed on and in contact with the high-k dielectric layer on at least one side of each gate electrode of the plurality of gates on the isolation feature;

unmasking the at least one gate and the at least two S/Ds on the fin; and

depositing the fill metal in each contact trench.

5. The method of claim 4, wherein the plurality of gates on the isolation feature and the at least one gate on the fin are formed in the same process;

the ILD over each S/D and the ILD between the plurality of gates on the isolation feature are removed in the same process; and

the fill metal between the plurality of gates on the isolation feature and in each contact trench are deposited in the same process.

6-8. -8. (canceled)

9. A semiconductor device, comprising:

a semiconductor substrate;

an isolation feature on the substrate;

a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and disposed on and in contact with at least one side of the gate electrode; and

a fill metal between the plurality of gates on the isolation feature, wherein the fill metal is in contact with the high-k dielectric layer on at least one side of at least one of the plurality of gates.

10. The semiconductor device of claim 9, wherein:

the isolation feature is in an inactive region of the semiconductor device.

11. The semiconductor device of claim 9, further comprising:

a fin in an active region on the semiconductor substrate;

at least one gate on the fin, wherein the at least one gate comprises a gate electrode, a high-k dielectric layer disposed between the gate electrode and the fin and disposed on and in contact with at least one side of the gate electrode, and a spacer disposed on and in contact with the high-k dielectric layer on at least one side of the gate electrode;

at least two sources/drains (S/Ds), each S/D disposed on and/or in the fin adjacent to the spacer on each side of the at least one gate; and

the fill metal disposed adjacent to both sides of the at least one gate on the fin and in contact with each S/D.

12-14. -14. (canceled)

15. A system, comprising:

a semiconductor device processing system to manufacture a semiconductor device; and

a processing controller operatively coupled to the semiconductor device processing system, the processing controller configured to control an operation of the semiconductor device processing system;

wherein the semiconductor device processing system is adapted to;

form an isolation feature on a semiconductor substrate;

form a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and disposed on and in contact with at least one side of the gate electrode; and

deposit a fill metal between the plurality of gates on the isolation feature, wherein the fill metal after deposition is in contact with the high-k dielectric layer on at least one side of at least one of the plurality of gates.

16. The system of claim 15, wherein the semiconductor device processing system is adapted to form the fill metal to contact the high-k dielectric layer on the at least one side of the gate electrode.

17. The system of claim 15, wherein the semiconductor device processing system is further adapted to:

form a fin in an active region on the semiconductor substrate;

form at least one gate on the fin, wherein the at least one gate comprises a gate electrode, a high-k dielectric layer disposed between the gate electrode and the fin and disposed on and in contact with at least one side of the gate electrode,

form a spacer disposed on and in contact with the high-k dielectric layer on at least one side of the gate electrode of the at least one gate on the fin and disposed on and in contact with the high-k dielectric layer on at least one side of each gate electrode of the plurality of gates on the isolation feature;

form at least two sources/drains (S/Ds), each S/D disposed on and/or in the fin adjacent to the spacer on each side of the at least one gate;

form an interlayer dielectric (ILD) over each S/D and between the plurality of gates on the isolation feature, wherein the ILD is disposed in contact with the spacer;

remove the ILD over each S/D and between the plurality of gates on the isolation feature, to yield a plurality of contact trenches each exposing either one of the S/Ds or the isolation feature;

mask the at least one gate and the at least two S/Ds on the fin;

remove the plurality of spacers disposed on and in contact with the high-k dielectric layer on at least one side of each gate electrode of the plurality of gates on the isolation feature;

unmask the at least one gate and the at least two S/Ds on the fin; and

deposit the fill metal in each contact trench.

18. The system of claim 17, wherein the semiconductor device processing system is adapted to form the plurality of gates on the isolation feature and the at least one gate on the fin in the same process;

remove the ILD over each S/D and the ILD between the plurality of gates on the isolation feature in the same process; and

deposit the fill metal between the plurality of gates on the isolation feature and in each contact trench in the same process.

19-20. -20. (canceled)