SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME

• US 20190312030A1
• Filed: 06/05/2019
• Published: 10/10/2019
• Est. Priority Date: 10/30/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Moon-Kyu, Song, Jae-Yeol, Na, Hoon-Joo, Hwang, Yoon-Tae, Yoon, Ki-Joong, Hyun, Sang-Jin
• Granted Patent: US 10,872,888 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02345 treatment by exposure to radiation, e.g. visible light
• CPC Class Codes: H01L 21/02356 treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/435 Resistive materials for field effect devices, e.g. resistive gate for MOSFET or MESFET
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 : with the body tied to the substrate
• CPC Class Codes: H01L 29/7854 : with rounded corners
• CPC Class Codes: H01L 29/7856 : with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence

Abstract

Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.

Claims

1. A semiconductor device comprising:

a fin-shaped active region protruding from a substrate;

a field insulating layer on the substrate, the field insulating layer being on a side of a lower portion of the fin-shaped active region and absent from an upper portion of the fin-shaped active region;

a gate insulating layer extending along an upper surface of the field insulating layer and three sides of the fin-shaped active region; and

a gate electrode structure on the gate insulating layer, the gate electrode structure comprising a silicon oxide layer spaced apart from the gate insulating layer and a barrier metal layer between the silicon oxide layer and the gate insulating layer,

wherein the three sides of the fin-shaped active region include top, right, and left sides of the fin-shaped active region.

2. The semiconductor device of claim 1, wherein the silicon oxide layer extends along a surface of the barrier metal layer.

3. The semiconductor device of claim 1, wherein the gate insulating layer comprises an interfacial layer extending along the three sides of the fin-shaped active region, and the interfacial layer comprises silicon oxide.

4. The semiconductor device of claim 3, wherein the gate insulating layer further comprises a high-k insulating material layer stacked on the interfacial layer.

5. The semiconductor device of claim 1, wherein the gate electrode structure further comprises a conductive layer on the silicon oxide layer.

6. The semiconductor device of claim 1, further comprising a channel layer between the substrate and the gate insulating layer.

7. The semiconductor device of claim 6, wherein the channel layer has a lattice constant different from a lattice constant of the substrate.

8. A semiconductor device comprising:

a fin-shaped active region protruding from a substrate;

a field insulating layer on the substrate, the field insulating layer being on a side of a lower portion of the fin-shaped active region and absent from an upper portion of the fin-shaped active region;

a first silicon oxide layer extending along a surface of the upper portion of the fin-shaped active region;

a high-k insulating layer on the first silicon oxide layer and the field insulating layer;

a barrier metal layer on the high-k insulating layer;

a second silicon oxide layer on the barrier metal layer, the barrier metal layer extending between the second silicon oxide layer and the high-k insulating layer, and the second silicon oxide layer extending along an upper surface of the field insulating layer; and

an upper gate electrode on the second silicon oxide layer, the upper gate electrode crossing the fin-shaped active region.

9. The semiconductor device of claim 8, wherein the second silicon oxide layer extends along a surface of the high-k insulating layer.

10. The semiconductor device of claim 8, further comprising a silicon layer between the barrier metal layer and the second silicon oxide layer.

11. A semiconductor device comprising:

a fin-shaped active region protruding from a substrate;

a gate insulating layer on the substrate and fin-shaped active region;

a lower gate electrode on the gate insulating layer, the lower gate electrode comprising a barrier metal layer;

a silicon oxide layer on the lower gate electrode; and

an upper gate electrode on the silicon oxide layer, the upper gate electrode having a thickness different from a thickness of the lower gate electrode.

12. The semiconductor device of claim 11, wherein the fin-shaped active region has top, right, and left sides;

and

wherein the lower gate electrode, the silicon oxide layer, and the upper gate electrode extend along the top, right, and left sides of the fin-shaped active region.

13. The semiconductor device of claim 12, wherein the thickness of the upper gate electrode is greater than the thickness of the lower gate electrode.

14. The semiconductor device of claim 12, further comprising an interlayer insulating layer on the substrate,

wherein the interlayer insulating layer comprises a trench, and

wherein the gate insulating layer, the lower gate electrode, the silicon oxide layer, and the upper gate electrode extend along a sidewall and a bottom surface of the trench.

15. The semiconductor device of claim 14, wherein the thickness of the lower gate electrode on the sidewall of the trench is different from the thickness of the upper gate electrode on the sidewall of the trench.