ROM Chip Manufacturing Structures Having Shared Gate Electrodes

• US 20190312031A1
• Filed: 06/17/2019
• Published: 10/10/2019
• Est. Priority Date: 07/10/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liaw, Jhon-Jhy
• Granted Patent: US 10,867,996 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 17/08 using semiconductor devices, e.g. bipolar elements G11C17/06, G11C17/14 take precedence
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/34 Source electrode or drain electrode programmed

Abstract

An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include first portions of first and second gate structures, respectively. The IC chip further includes a strap cell disposed between the first and second ROM cells. The strap cell includes second portions of the first and second gate structures. The first gate structure is physically separated from the second gate structure.

Claims

1. A device comprising:

a read-only-memory (ROM) array having a first row comprising;

a plurality of first ROM cells;

a plurality of second ROM cells;

a first strap cell disposed between the first ROM cells and the second ROM cells;

a first gate structure extending through each of the first ROM cells, a first end of the first gate structure being disposed in the first strap cell;

a second gate structure extending through each of the second ROM cells, a second end of the second gate structure being disposed in the first strap cell;

a third gate structure extending through each of the first ROM cells, the first strap cell, and the second ROM cells;

a first conductive feature electrically coupled to the first gate structure and the second gate structure; and

a second conductive feature electrically coupled to the third gate structure,

wherein the first conductive feature and the second conductive feature are disposed in different columns of the ROM array.

2. The device of claim 1 further comprising:

a word line electrically coupled to the first conductive feature.

3. The device of claim 2, wherein the first conductive feature comprises:

a first gate contact physically contacting the first gate structure;

a second gate contact physically contacting the second gate structure; and

a conductive line electrically coupled to the first gate contact, the second gate contact, and the word line.

4. The device of claim 3 further comprising:

a first dielectric layer surrounding the first gate structure, the second gate structure, the first gate contact, and the second gate contact;

a second dielectric layer over the first dielectric layer, the second dielectric layer surrounding the conductive line; and

a third dielectric layer over the second dielectric layer, the third dielectric layer surrounding the word line.

5. The device of claim 2, wherein the first conductive feature comprises:

a shared gate contact physically contacting the first gate structure and the second gate structure; and

a conductive line electrically coupled to the shared gate contact and the word line.

6. The device of claim 5 further comprising:

a first dielectric layer surrounding the first gate structure, the second gate structure, and the shared gate contact;

a second dielectric layer over the first dielectric layer, the second dielectric layer surrounding the conductive line; and

a third dielectric layer over the second dielectric layer, the third dielectric layer surrounding the word line.

7. The device of claim 1, wherein a first quantity of the first ROM cells is equal to a second quantity of the second ROM cells.

8. The device of claim 1 further comprising:

a ground voltage supply line electrically coupled to the second conductive feature.

9. A device comprising:

a read-only-memory (ROM) array having a first row comprising;

a first strap cell;

a second strap cell;

a plurality of first ROM cells disposed between the first strap cell and the second strap cell; and

a first gate structure extending through each of the plurality of first ROM cells, a first end of the first gate structure being disposed in the first strap cell;

a second gate structure extending through each of the plurality of first ROM cells, a second end of the second gate structure being disposed in the second strap cell, the first gate structure being substantially parallel to the second gate structure;

a first conductive feature disposed in the first strap cell, the first conductive feature being coupled to the first gate structure; and

a second conductive feature disposed in the second strap cell, the second conductive feature being coupled to the second gate structure.

10. The device of claim 9, wherein the second gate structure extends through the first strap cell.

11. The device of claim 9, wherein a third end of the first gate structure is disposed in the second strap cell.

12. The device of claim 9, wherein the ROM array further comprises:

a ground voltage supply line, the second conductive feature electrically coupling the ground voltage supply line to the second gate structure.

13. The device of claim 9, wherein the ROM array further comprises:

a word line, the first conductive feature electrically coupling the word line to the first gate structure.

14. The device of claim 13, wherein the ROM array further comprises:

a third strap cell;

a plurality of second ROM cells disposed between the second strap cell and the third strap cell;

a third gate structure extending through each of the plurality of second ROM cells, a third end of the third gate structure being disposed in the third strap cell; and

a third conductive feature disposed in the third strap cell, the third conductive feature being coupled to the third gate structure, the third conductive feature electrically coupling the word line to the third gate structure.

15. The device of claim 14 further comprising:

a first dielectric layer surrounding the first gate structure, the second gate structure, and the third gate structure; and

a second dielectric layer over the first dielectric layer, the second dielectric layer surrounding the word line.

16. A device comprising:

a read-only-memory (ROM) array having a first row comprising;

a first strap cell;

a second strap cell;

a plurality of first ROM cells disposed between the first strap cell and the second strap cell; and

a first gate structure extending through each of the plurality of first ROM cells, a first end of the first gate structure being disposed in the first strap cell, a second end of the first gate structure being disposed in the second strap cell,

wherein the first row of the ROM array runs in a direction substantially parallel to a lengthwise direction of the first gate structure.

17. The device of claim 16, wherein the ROM array further comprises:

a third strap cell;

a plurality of second ROM cells disposed between the second strap cell and the third strap cell; and

a second gate structure extending through each of the plurality of second ROM cells, a third end of the second gate structure being disposed in the third strap cell, a fourth end of the second gate structure being disposed in the second strap cell,

wherein the first row of the ROM array runs in a direction substantially parallel to a lengthwise direction of the second gate structure.

18. The device of claim 17 further comprising:

a first gate contact physically contacting a top surface of the first gate structure;

a second gate contact physically contacting a top surface of the second gate structure;

a conductive line electrically coupling the first gate contact to the second gate contact; and

a word line electrically coupled to the conductive line.

19. The device of claim 17 further comprising:

a shared gate contact physically contacting a top surface of the first gate structure, a top surface of the second gate structure, the second end of the first gate structure, and the fourth end of the second gate structure;

a conductive line electrically coupled to the shared gate contact; and

a word line electrically coupled to the conductive line.

20. The device of claim 16, wherein the ROM array further comprises:

a second gate structure extending through each of the first strap cell, the second strap cell, and the first ROM cells, the second gate structure being permanently connected to ground.