PARTIALLY DISPOSED GATE LAYER INTO THE TRENCHES
First Claim
1. A system, comprising:
- a substrate layer having an outer surface;
a plurality of trenches extending from the outer surface into the substrate layer;
a plurality of active regions, each active region positioned between a different pair of consecutive trenches of the plurality of trenches;
a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions; and
a floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.
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Accused Products
Abstract
In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.
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Citations
20 Claims
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1. A system, comprising:
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a substrate layer having an outer surface; a plurality of trenches extending from the outer surface into the substrate layer; a plurality of active regions, each active region positioned between a different pair of consecutive trenches of the plurality of trenches; a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions; and a floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method, comprising:
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obtaining a wafer including a plurality of floating gate layers; measuring thicknesses of the plurality of floating gate layers; calculating a floating gate thickness variation value using the measured floating gate layer thicknesses and a target value; etching, at least in part based on the floating gate thickness variation value, a plurality of shallow trench isolation structures; and increasing, based on the floating gate thickness variation value, an oxide etch time of the wafer. - View Dependent Claims (8, 9, 11)
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10. (canceled)
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12. A method, comprising:
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obtaining a substrate layer having an outer surface and comprising a plurality of shallow trench isolation structures extending from a first surface above the outer surface into the substrate layer, wherein a first dielectric layer interfaces with the outer surface, and wherein a plurality of floating gate layers are positioned on the first dielectric layer; measuring a thickness of each of the plurality of floating gate layers; calculating a floating gate thickness variation value using the measured thicknesses of the plurality of floating gate layers with a target value; and etching the plurality of shallow trench isolation structures based on the floating gate thickness variation value. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification