SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
First Claim
1. A semiconductor device, comprising:
- a plurality of lower gate electrodes on a substrate in a first direction substantially perpendicular to a top surface of the substrate;
a plurality of upper gate electrodes on the plurality of lower gate electrodes in the first direction, the plurality of upper gate electrodes spaced apart from one another in the first direction; and
a plurality of channel structures, each channel structure of the plurality of channel structures extending through both the plurality of lower gate electrodes and the plurality of upper gate electrodes in the first direction, each channel structure of the plurality of channel structures includinga lower channel structure penetrating through the plurality of lower gate electrodes,an upper channel structure penetrating through the plurality of upper gate electrodes, anda landing pad interconnecting the lower channel structure to the upper channel structure,wherein a first channel structure of the plurality of channel structures includes a first landing pad having a horizontal width substantially greater than a horizontal width of a first lower channel structure of the first channel structure at a first vertical level,wherein a second channel structure of the plurality of channel structures that is closest to the first channel structure of a remainder of the plurality of channel structures includes a second landing pad having a horizontal width substantially greater than the horizontal width of a second lower channel structure of the second channel structure at a second vertical level, the second vertical level lower than the first vertical level.
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Accused Products
Abstract
A semiconductor device includes lower gate electrodes on a substrate in a first direction substantially perpendicular to a top surface of the substrate, upper gate electrodes on the lower gate electrodes in the first direction, and channel structures extending through the lower and upper gate electrodes in the first direction. Each channel structure includes a lower channel structure, an upper channel structure, and a landing pad interconnecting the lower and upper channel structures. The first channel structure includes a first landing pad having a horizontal width substantially greater than that of the lower channel structure of the first channel structure at a first vertical level. The second channel structure located closest to the first channel structure includes a second landing pad having a horizontal width substantially greater than that of the lower channel structure of the second channel structure at a second vertical level lower than the first vertical level.
12 Citations
20 Claims
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1. A semiconductor device, comprising:
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a plurality of lower gate electrodes on a substrate in a first direction substantially perpendicular to a top surface of the substrate; a plurality of upper gate electrodes on the plurality of lower gate electrodes in the first direction, the plurality of upper gate electrodes spaced apart from one another in the first direction; and a plurality of channel structures, each channel structure of the plurality of channel structures extending through both the plurality of lower gate electrodes and the plurality of upper gate electrodes in the first direction, each channel structure of the plurality of channel structures including a lower channel structure penetrating through the plurality of lower gate electrodes, an upper channel structure penetrating through the plurality of upper gate electrodes, and a landing pad interconnecting the lower channel structure to the upper channel structure, wherein a first channel structure of the plurality of channel structures includes a first landing pad having a horizontal width substantially greater than a horizontal width of a first lower channel structure of the first channel structure at a first vertical level, wherein a second channel structure of the plurality of channel structures that is closest to the first channel structure of a remainder of the plurality of channel structures includes a second landing pad having a horizontal width substantially greater than the horizontal width of a second lower channel structure of the second channel structure at a second vertical level, the second vertical level lower than the first vertical level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A semiconductor device, comprising:
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a plurality of lower gate electrodes on a substrate in a first direction substantially perpendicular to a top surface of the substrate; a plurality of upper gate electrodes on the plurality of lower gate electrodes in the first direction, the plurality of upper gate electrodes spaced apart from one another in the first direction; and a plurality of channel structures, each channel structure of the plurality of channel structures extending through both the plurality of lower gate electrodes and the plurality of upper gate electrodes in the first direction, each channel structure of the plurality of channel structures including a lower channel structure penetrating through the plurality of lower gate electrodes, an upper channel structure penetrating through the plurality of upper gate electrodes, and a landing pad interconnecting the lower channel structure to the upper channel structure, wherein a first channel structure of the plurality of channel structures includes a first landing pad having a largest horizontal width of the first landing pad at a first vertical level, wherein a second channel structure of the plurality of channel structures that is closest to the first channel structure includes a second landing pad having a largest horizontal width of the second landing pad at a second vertical level that is substantially lower than the first vertical level. - View Dependent Claims (13, 14, 15)
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16. A semiconductor device, comprising:
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a plurality of lower gate electrodes on a substrate in a first direction substantially perpendicular to a top surface of the substrate; a plurality of upper gate electrodes on the plurality of lower gate electrodes in the first direction, the plurality of upper gate electrodes spaced apart from one another in the first direction; a first channel structure that extends in the first direction and includes a first lower channel structure penetrating through the lower gate electrodes, a first upper channel structure penetrating through the upper gate electrodes, and a first landing pad between the first lower channel structure and the first upper channel structure; and a second channel structure that extends in the first direction and is spaced apart from the first channel structure in a second direction parallel to the top surface of the substrate and includes a second lower channel structure penetrating through the lower gate electrodes, a second upper channel structure penetrating through the upper gate electrodes, and a second landing pad between the second lower channel structure and the second upper channel structure, wherein a bottom surface of the first upper channel structure contacts the first landing pad at a first vertical level and a bottom surface of the second upper channel structure contacts the second landing pad at a second vertical level substantially lower than the first vertical level. - View Dependent Claims (17, 18, 19, 20)
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Specification