SEMICONDUCTOR DEVICE

• US 20190312105A1
• Filed: 02/20/2019
• Published: 10/10/2019
• Est. Priority Date: 04/04/2018
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: SAKURAI, Yosuke, ONOZAWA, Yuichi, NAKAGAWA, Akio
• Granted Patent: US 10,916,628 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/0664 Vertical bipolar transistor in combination with diodes
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/083 Anode or cathode regions of thyristors or gated bipolar-mode devices
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes

Abstract

Provided is a semiconductor device including a drift region having a first conductivity type provided on a semiconductor substrate; a plurality of trench portions provided above the drift region, on a top surface side of the semiconductor substrate; a base region having a second conductivity type provided in a mesa portion sandwiched between the plurality of trench portions, in the semiconductor substrate; an emitter region having the first conductivity type provided above the base region, on a top surface of the mesa portion; and a contact region having the second conductivity type and a higher doping concentration than the base region, provided adjacent to the emitter region on the top surface of the mesa portion, wherein a mesa width of the mesa portion is less than or equal to 100 nm, and a bottom end of the contact region is shallower than a bottom end of the emitter region.

Claims

1. A semiconductor device comprising:

a drift region having a first conductivity type provided on a semiconductor substrate;

a plurality of trench portions provided above the drift region, on a top surface side of the semiconductor substrate;

a base region having a second conductivity type provided in a mesa portion sandwiched between the plurality of trench portions, in the semiconductor substrate;

an emitter region having the first conductivity type provided above the base region, on a top surface of the mesa portion; and

a contact region having the second conductivity type and a higher doping concentration than the base region, provided adjacent to the emitter region on the top surface of the mesa portion, wherein

a mesa width of the mesa portion is less than or equal to 100 nm, and

a bottom end of the contact region is shallower than a bottom end of the emitter region.

2. The semiconductor device according to claim 1, wherein

the plurality of trench portions include gate conducting portions, and

the bottom end of the contact region is deeper than top ends of the gate conducting portions.

3. The semiconductor device according to claim 1, comprising:

a plurality of the emitter regions arranged on the top surface of the mesa portion; and

a carrier path layer having a second conductivity type and a higher doping concentration than the base region, extending in a depth direction of the semiconductor substrate from the top surface of the mesa portion between adjacent emitter regions.

4. The semiconductor device according to claim 3, wherein

the carrier path layer has the same doping concentration as the contact region.

5. The semiconductor device according to claim 3, wherein

a depth of a bottom end of the carrier path layer is greater than or equal to an interval between the carrier path layer and the emitter region at the top surface of the mesa portion.

6. The semiconductor device according to claim 3, wherein

the carrier path layer is provided at a position including at least a center between adjacent emitter regions, at the top surface of the mesa portion.

7. The semiconductor device according to claim 3, wherein

the carrier path layer occupies a region that is greater than or equal to 25% and less than or equal to 75% of a region between adjacent emitter regions, at the top surface of the mesa portion.

8. A semiconductor device comprising:

a drift region having a first conductivity type provided on a semiconductor substrate;

a plurality of trench portions provided above the drift region, on a top surface side of the semiconductor substrate;

a base region having a second conductivity type provided in a mesa portion sandwiched between the plurality of trench portions, in the semiconductor substrate;

a plurality of emitter regions having the first conductivity type arranged on a top surface of the mesa portion; and

a carrier path layer having a second conductivity type and a higher doping concentration than the base region, extending from the top surface of the mesa portion to the drift region between adjacent emitter regions among the plurality of emitter regions, wherein

a mesa width of the mesa portion is less than or equal to 100 nm, and

the carrier path layer occupies the entire region between adjacent emitter regions among the plurality of emitter regions, at the top surface of the mesa portion.