SEMICONDUCTOR DEVICE AND POWER CONVERTER

• US 20190312113A1
• Filed: 01/14/2019
• Published: 10/10/2019
• Est. Priority Date: 04/05/2018
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: CHEN, Ze
• Granted Patent: US 10,872,959 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H02M 7/003 Constructional details, e.g. physical layout, assembly, wiring or busbar connections
• CPC Class Codes: H02M 7/53871 with automatic control of output voltage or current
• CPC Class Codes: H02P 27/08 with pulse width modulation

Abstract

A semiconductor device includes gate trenches and dummy gate trenches formed on the upper surface side of a semiconductor substrate, gate electrodes embedded in the gate trenches, dummy gate electrodes embedded in the dummy gate trenches, a channel layer formed in the surface portion on the upper surface side of the semiconductor substrate, a carrier storage layer formed below the channel layer, and a collector layer formed on the lower surface side of the semiconductor substrate. A relationship D4<D1<D3<D2 holds true, where D1 is the depth of the bottoms of the gate electrodes, D2 is the depth of the bottoms of the dummy gate electrodes, D3 is the depth of the bottom of the carrier storage layer, and D4 is the depth of the junction between the channel layer and the carrier storage layer.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

gate trenches formed on an upper surface side of the semiconductor substrate;

gate electrodes embedded in the gate trenches;

a gate insulating film interposed between the gate electrodes and the semiconductor substrate;

a channel layer of a second conductivity type formed in a surface portion on the upper surface side of the semiconductor substrate;

a contact layer of the second conductivity type formed in a surface portion of the channel layer and having a higher peak impurity concentration than the channel layer;

an emitter layer of the first conductivity type formed adjacent to the gate trenches in the surface portion of the channel layer;

a carrier storage layer of the first conductivity type formed below the channel layer;

a collector layer of the second conductivity type formed on a lower surface side of the semiconductor substrate;

a dummy gate trench formed between each two adjacent ones of the gate trenches on the upper surface side of the semiconductor substrate;

dummy gate electrodes embedded in the dummy gate trenches; and

a dummy gate insulating film interposed between the dummy gate electrodes and the semiconductor substrate,

wherein a relationship D4<

D1<

D3<

D2 holds true,

where D1 is a depth of bottoms of the gate electrodes, D2 is a depth of bottoms of the dummy gate electrodes, D3 is a depth of a bottom of the carrier storage layer, and D4 is a depth of a junction between the channel layer and the carrier storage layer.

2. The semiconductor device according to claim 1, wherein

an interval between two adjacent ones of the dummy gate electrodes that sandwich at least one of the gate electrodes therebetween is less than or equal to 15 mm.

3. The semiconductor device according to claim 1, wherein

the dummy gate electrodes are electrically connected to the contact layer.

4. The semiconductor device according to claim 2, wherein

the dummy gate electrodes are electrically connected to the contact layer.

5. A power converter comprising:

a main converter circuit to convert input power and output converted power, the main converter circuit including the semiconductor device according to claim 1;

a drive circuit to output a driving signal for driving the semiconductor device to the semiconductor device; and

a control circuit to output a control signal for controlling the drive circuit to the drive circuit.

6. A power converter comprising:

a main converter circuit to convert input power and output converted power, the main converter circuit including the semiconductor device according to claim 2;

a drive circuit to output a driving signal for driving the semiconductor device to the semiconductor device; and

a control circuit to output a control signal for controlling the drive circuit to the drive circuit.

7. A power converter comprising:

a main converter circuit to convert input power and output converted power, the main converter circuit including the semiconductor device according to claim 3;

a drive circuit to output a driving signal for driving the semiconductor device to the semiconductor device; and

a control circuit to output a control signal for controlling the drive circuit to the drive circuit.

8. A power converter comprising:

a main converter circuit to convert input power and output converted power, the main converter circuit including the semiconductor device according to claim 4;

a drive circuit to output a driving signal for driving the semiconductor device to the semiconductor device; and

a control circuit to output a control signal for controlling the drive circuit to the drive circuit.

9. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type;

gate trenches formed on an upper surface side of the semiconductor substrate;

gate electrodes embedded in the gate trenches;

a gate insulating film interposed between the gate electrodes and the semiconductor substrate;

a channel layer of a second conductivity type formed in a surface portion on the upper surface side of the semiconductor substrate;

a contact layer of the second conductivity type formed in a surface portion of the channel layer and having a higher peak impurity concentration than the channel layer;

an emitter layer of the first conductivity type formed adjacent to the gate trenches in the surface portion of the channel layer;

a carrier storage layer of the first conductivity type formed below the channel layer; and

a collector layer of the second conductivity type formed on a lower surface side of the semiconductor substrate,

wherein some of the gate trenches are formed shallower than the other gate trenches, and

a relationship D4<

D1<

D3<

D2 holds true,

where D1 is a depth of bottoms of gate electrodes embedded in shallow gate trenches, D2 is a depth of bottoms of gate electrodes embedded in deep gate trenches, D3 is a depth of a bottom of the carrier storage layer, and D4 is a depth of a bottom of a junction between the channel layer and the carrier storage layer.

10. The semiconductor device according to claim 9, wherein

an interval between gate electrodes embedded in two adjacent ones of the deep gate trenches that sandwich at least one of the shallow gate trenches therebetween is less than or equal to 15 μ

m.

11. The semiconductor device according to claim 9, wherein

the gate electrodes are electrically connected to the contact layer.

12. The semiconductor device according to claim 10, wherein

the gate electrodes are electrically connected to the contact layer.

13. A power converter comprising:

a main converter circuit to convert input power and output converted power, the main converter circuit including the semiconductor device according to claim 9;

a drive circuit to output a driving signal for driving the semiconductor device to the semiconductor device; and

a control circuit to output a control signal for controlling the drive circuit to the drive circuit.

14. A power converter comprising:

a main converter circuit to convert input power and output converted power, the main converter circuit including the semiconductor device according to claim 10;

a drive circuit to output a driving signal for driving the semiconductor device to the semiconductor device; and

a control circuit to output a control signal for controlling the drive circuit to the drive circuit.

15. A power converter comprising:

a main converter circuit to convert input power and output converted power, the main converter circuit including the semiconductor device according to claim 11;

a drive circuit to output a driving signal for driving the semiconductor device to the semiconductor device; and

a control circuit to output a control signal for controlling the drive circuit to the drive circuit.

16. A power converter comprising:

a main converter circuit to convert input power and output converted power, the main converter circuit including the semiconductor device according to claim 12;

a drive circuit to output a driving signal for driving the semiconductor device to the semiconductor device; and

a control circuit to output a control signal for controlling the drive circuit to the drive circuit.