Methods of Manufacturing Semiconductor Devices with a Deep Barrier Layer

• US 20190312127A1
• Filed: 04/09/2018
• Published: 10/10/2019
• Est. Priority Date: 04/09/2018
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Karmous, Alim
• Granted Patent: US 10,608,099 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of manufacturing a semiconductor device includes: etching a plurality of trenches to a first depth in a semiconductor substrate; doping a region of the semiconductor substrate surrounding a bottom of the trenches at the first depth to form a doped region in the semiconductor substrate; after the doped region is formed, etching the plurality of trenches deeper into the semiconductor substrate to a second depth greater than the first depth, adjacent ones of the trenches being separated from one another by a semiconductor mesa; and forming a body region above the doped region in the semiconductor mesas.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

etching a plurality of trenches to a first depth in a semiconductor substrate;

doping a region of the semiconductor substrate surrounding a bottom of the trenches at the first depth to form a doped region in the semiconductor substrate;

after the doped region is formed, etching the plurality of trenches deeper into the semiconductor substrate to a second depth greater than the first depth, adjacent ones of the trenches being separated from one another by a semiconductor mesa; and

forming a body region above the doped region in the semiconductor mesas.

2. The method of claim 1, wherein the body region is doped p-type, and wherein the doped region is a hole potential barrier.

3. The method of claim 1, wherein the body region is doped n-type, and wherein the doped region is an electron potential barrier.

4. The method of claim 1, wherein etching the plurality of trenches to the first depth in the semiconductor substrate comprises:

forming a structured trench etch hard mask on a first main surface of the semiconductor substrate; and

etching the plurality of trenches to the first depth in the semiconductor substrate through openings in the structured trench etch hard mask.

5. The method of claim 1, further comprising:

before the doped region is formed, forming a protection layer or stack of protection layers on side walls and the bottom of the trenches at the first depth.

6. The method of claim 5, wherein forming the doped region comprises:

implanting a dopant species through the protection layer or stack of protection layers at the bottom of the trenches at the first depth; and

annealing the semiconductor substrate to diffuse and activate the implanted dopant species.

7. The method of claim 5, wherein forming the doped region comprises:

removing the protection layer or stack of protection layers from the bottom of the trenches at the first depth to expose the trench bottoms;

implanting a dopant species into the exposed trench bottoms; and

annealing the semiconductor substrate to diffuse and activate the implanted dopant species.

8. The method of claim 5, wherein forming the doped region comprises:

removing the protection layer or stack of protection layers from the bottom of he trenches at the first depth to expose the trench bottoms;

depositing a dopant source material on the exposed trench bottoms; and

diffusing a dopant species from the dopant source material and into the region of the semiconductor substrate surrounding the bottom of the trenches at the first depth.

9. The method of claim 5, further comprising:

after the doped region is formed, removing the protection layer or stack of protection layers from the trenches.

10. The method of claim 9, wherein the protection layer or stack of protection layers is removed from the trenches after etching the trenches deeper into the semiconductor substrate to the second depth, so that the sidewalls of the trenches have a step at the first depth.

11. The method of claim 5, wherein the protection layer or stack of protection layers comprises a silicon oxide layer.

12. The method of claim 5, wherein the protection layer or of protection layers comprises a silicon nitride layer.

13. The method of claim 5, wherein the protection layer or stack of protection layers comprises a stack of one or more silicon oxide layers and one or more silicon nitride layers.

14. The method of claim 1, wherein the doped region has a peak doping concentration of at least 5 E16 cm⁻

3.

15. The method of claim 1, further comprising:

after etching the plurality of trenches deeper into the semiconductor substrate to the second depth, forming a gate dielectric and a gate electrode in the trenches,

wherein the gate dielectric insulates the gate electrode from the surrounding semiconductor substrate.

16. A semiconductor device, comprising:

a semiconductor substrate having a first main surface;

a plurality of trenches extending from the first main surface into the semiconductor substrate;

semiconductor mesas disposed between adjacent ones of the trenches;

a hole or electron potential barrier formed in the semiconductor mesas; and

a body region formed above the hole or electron potential barrier in the semiconductor mesas,

wherein the hole or electron potential barrier has a peak doping concentration of at least 5 E16 cm<sup>−

3</sup>.

17. The semiconductor device of claim 16, wherein the hole or electron potential barrier is doped n-type and is a hole potential barrier.

18. The semiconductor device of claim 16, wherein the hole or electron potential barrier is doped p-type and is an electron potential barrier.

19. A method of manufacturing a semiconductor device, the method comprising:

etching a trench to a first depth in a semiconductor substrate;

doping a region of the semiconductor substrate surrounding a bottom of the trench at the first depth to form an n-type hole potential barrier; and

after the n-type hole potential barrier is formed, etching the trench deeper into the semiconductor substrate to a second depth greater than the first depth.

20. The method of claim 19, further comprising:

before the n-type hole potential barrier if formed, forming a protection layer or stack of protection layers on sidewalls and the bottom of the trench at the first depth.