INTEGRATED CIRCUIT DEVICE

• US 20190312130A1
• Filed: 10/22/2018
• Published: 10/10/2019
• Est. Priority Date: 04/10/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Min-seong, Kim, Il-ryong, Yeo, Kyoung-hwan, Chung, Jae-yup
• Granted Patent: US 10,672,890 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

An integrated circuit device includes a substrate including a first device region and a second device region; a first fin separation insulating portion on the first device region; a pair of first fin-type active regions spaced from each other with the first fin separation insulating portion therebetween in the first device region and collinearly extending in a first horizontal direction; a second fin separation insulating portion extending in a second horizontal direction over the first device region and the second device region; and a pair of second fin-type active regions spaced from each other with the second fin separation insulating portion therebetween and collinearly extending in the first horizontal direction, wherein the first fin separation insulating portion and the second fin separation insulating portion vertically overlap each other.

Claims

1. An integrated circuit device comprising:

a substrate comprising a first device region and a second device region spaced from the first device region;

a device isolation region between the first device region and the second device region;

a first fin separation insulating portion arranged on the first device region and having a first width in a first horizontal direction;

a pair of first fin-type active regions in the first device region, the pair of first fin-type active regions including a first element and a second element spaced from each other, with the first fin separation insulating portion between the first element and the second element, the first element and the second element collinearly extending in the first horizontal direction;

a second fin separation insulating portion extending in a second horizontal direction over the first device region, the device isolation region, and the second device region, and having a second width in the first horizontal direction that is less than the first width, the second horizontal direction crossing the first horizontal direction; and

a pair of second fin-type active regions spaced from each other with the second fin separation insulating portion therebetween in the second device region and collinearly extending in the first horizontal direction,

wherein the first fin separation insulating portion and the second fin separation insulating portion vertically overlap each other.

2. The integrated circuit device of claim 1, wherein the first fin separation insulating portion and the second fin separation insulating portion contact each other on the first device region.

3. The integrated circuit device of claim 1, wherein a lowermost surface of the first fin separation insulating portion is at a different vertical level than a lowermost surface of the second fin separation insulating portion.

4. The integrated circuit device of claim 1, wherein an uppermost surface of the first fin separation insulating portion is at a different vertical level than an uppermost surface of the second fin separation insulating portion.

5. The integrated circuit device of claim 1, further comprising:

a gate structure extending in the second horizontal direction over the first device region, the device isolation region, and the second device region,

wherein the second fin separation insulating portion extends parallel to the gate structure over the first device region, the device isolation region, and the second device region.

6. The integrated circuit device of claim 5, wherein an uppermost surface of the first fin separation insulating portion is at a lower vertical level than an uppermost surface of the pair of first fin-type active regions, and

an uppermost surface of the second fin separation insulating portion is at a vertical level higher than an uppermost surface of the gate structure.

7. The integrated circuit device of claim 1, wherein the second fin separation insulating portion comprises:

an upper insulating portion over the first device region, the device isolation region, and the second device region, the upper insulating portion extending in the second horizontal direction; and

a lower insulating portion protruding from the upper insulating portion toward the substrate and arranged between the first element and the second element of the pair of second fin-type active regions.

8. The integrated circuit device of claim 1, wherein the second fin separation insulating portion is configured to extend between the pair of first fin-type active regions over the first device region.

9. The integrated circuit device of claim 1, wherein the first fin separation insulating portion comprises a first insulating film,

the second fin separation insulating portion comprises a second insulating film having a different composition from the first insulating film, and

the first insulating film and the second insulating film contact each other in the first device region.

10. An integrated circuit device comprising:

a substrate comprising a first device region and a second device region spaced from the first region;

a device isolation region between the first device region and the second device region;

a first fin separation insulating portion on the first device region;

a plurality of pairs of first fin-type active regions in the first device region, each of the plurality of pairs including a first element and a second element spaced from the first element with the first fin separation insulating portion therebetween, the first element collinearly extending with the second element in a first horizontal direction;

a plurality of second fin separation insulating portions extending in a second horizontal direction over the first device region, the device isolation region, and the second device region, and spaced apart from each other, the second horizontal direction crossing the first horizontal direction; and

a plurality of second fin-type active regions in the second device region, the plurality of second fin-type active regions arranged in a straight line extending in a direction across the plurality of second fin separation insulating portions,

wherein the first fin separation insulating portion and the plurality of second fin separation insulating portions vertically overlap each other.

11. The integrated circuit device of claim 10, wherein a width of each of the plurality of second fin separation insulating portions in the first horizontal direction is less than a width of the first fin separation insulating portion in the first horizontal direction.

12. The integrated circuit device of claim 10, wherein the first fin separation insulating portion comprises a first side wall and a second side wall facing opposite to the first side wall in the first horizontal direction,

wherein one second fin separation insulating portion from among the plurality of second fin separation insulating portions contacts the first side wall, and another second fin separation insulating portion from among the plurality of second fin separation insulating portions contacts the second side wall.

13. The integrated circuit device of claim 10, wherein a vertical length of each of the plurality of second fin separation insulating portions is greater than a vertical length of the first fin separation insulating portion.

14. The integrated circuit device of claim 10, further comprising:

a gate structure extending in the second horizontal direction over the first device region, the device isolation region, and the second device region;

a first insulating spacer covering a side wall of the gate structure; and

a second insulating spacer covering side walls of the plurality of second fin separation insulating portions,

wherein a vertical length of the second insulating spacer is less than a vertical length of the first insulating spacer.

15. The integrated circuit device of claim 10, wherein the first device region includes an NMOS transistor region, and

the second device region includes a PMOS transistor region.

16. An integrated circuit device comprising:

a substrate comprising a first device region and a second device region spaced apart from each other;

a first fin separation insulating portion over the first device region;

a pair of first fin-type active regions in the first device region, the pair of first fin-type active regions including a first element and a second element spaced from the first element with the first fin separation insulating portion therebetween, the first element collinearly extending with the second element in a first horizontal direction;

a device isolation region;

a plurality of second fin separation insulating portions covering an upper surface of the first fin separation insulating portion and vertically overlapping the first fin separation insulating portion, the plurality of second fin separation insulating portions extending in a second horizontal direction from an upper portion of the first device region to an upper portion of the second device region through the device isolation region, the second horizontal direction crossing the first horizontal direction; and

a plurality of second fin-type active regions in the second device region, the plurality of second fin-type active regions spaced from each other with the plurality of second fin separation insulating portions therebetween, the plurality of second fin-type active regions collinearly extending in the first horizontal direction.

17. The integrated circuit device of claim 16, wherein a lowermost surface of the plurality of second fin separation insulating portions is at a different vertical level than that of lowermost surface of the first fin separation insulating portion.

18. The integrated circuit device of claim 16, further comprising:

a gate structure spaced apart from the plurality of second fin separation insulating portions in the first horizontal direction and extending parallel to the plurality of second fin separation insulating portions,

wherein an uppermost surface of the plurality of second fin separation insulating portions is at a vertical level that is higher than an uppermost surface of the gate structure, and a lowermost surface of the plurality of second fin separation insulating portions is at a vertical level that is substantially the same as or lower than a lowermost surface of the first fin separation insulating portion.

19. The integrated circuit device of claim 18, further comprising a dummy gate structure covering the first fin separation insulating portion over the first device region,

wherein the dummy gate structure is integrally connected to the gate structure extending over the first device region.

20. The integrated circuit device of claim 16, wherein the first fin separation insulating portion vertically overlaps at least three second fin separation insulating portions.