HIGH-ELECTRON-MOBILITY TRANSISTOR WITH BURIED INTERCONNECT

• US 20190312137A1
• Filed: 06/24/2019
• Published: 10/10/2019
• Est. Priority Date: 12/02/2016
• Status: Active Grant

• Current Assignee: Vishay-Siliconix
• Original Assignee: Vishay-Siliconix
• Inventors: SHIBIB, Ayman, TERRILL, Kyle, DING, Yongping, YANG, Jinman
• Granted Patent: US 10,665,711 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/42312 Gate electrodes for field effect devices
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

A high-electron-mobility transistor (HEMT) includes a substrate layer of silicon, a first contact disposed on a first surface of the substrate layer, and a number of layers disposed on a second surface of the substrate layer opposite the first surface. A second contact and a gate contact are disposed on those layers. A trench containing conducting material extends completely through the layers and into the substrate layer. In an embodiment of the HEMT, the first contact is a drain contact and the second contact is a source contact. In another embodiment of the HEMT, the first contact is a source contact and the second contact is a drain contact.

Claims

1. A method of fabricating a high-electron-mobility transistor (HEMT), the method comprising:

forming a first contact on a first surface of a substrate layer;

forming a buffer layer on a second surface of the substrate layer, wherein the second surface is opposite the first surface;

forming a first layer comprising gallium adjacent to the buffer layer;

forming a second layer comprising gallium adjacent to the first layer, wherein a two-dimensional electron gas (2DEG) layer is formed within the first layer at a junction with the second layer, wherein the 2DEG layer has an opening;

forming a second contact on the second layer;

forming a gate contact on the second layer;

forming a trench that has sidewalls that extend completely through the second layer, the 2DEG layer, the first layer, and the buffer layer and into the substrate layer, wherein the trench has a bottom within the substrate layer;

lining the sidewalls of the trench at the first layer, the buffer layer, and the first layer with an insulating material; and

depositing conducting material into the trench, wherein the conducting material in the trench is in contact with the substrate layer through at the bottom of the trench and wherein the conducting material in the trench is in contact with the second layer and with the 2DEG layer.

2. The method of claim 1, wherein the first contact comprises a source contact, and wherein the second contact comprises a drain contact.

3. The method of claim 2, further comprising, prior to forming the trench, forming a spacer comprising an insulating material on the second layer next to the gate contact, wherein the trench is then formed next to the spacer.

4. The method of claim 2, further comprising:

forming a first field plate;

forming a second field plate connected to the drain contact; and

forming a passivation layer on the second layer and around the gate contact and the second contact, wherein the gate contact is separated from the first field plate by a region of the passivation layer, and wherein the first field plate and the second field plate are disposed within the passivation layer.

5. The method of claim 4, further comprising forming a metal interconnect from the drain contact through and out of the passivation layer.

6. The method of claim 1, wherein the first contact comprises a drain contact, and wherein the second contact comprises a source contact.

7. The method of claim 6, further comprising:

forming a field plate connected to the source contact; and

forming a passivation layer on the second layer and around the gate contact, wherein the gate contact is separated from the field plate by a region of the passivation layer and wherein the field plate is disposed within the passivation layer.

8. The method of claim 7, further comprising forming a metal interconnect from the source contact through and out the passivation layer.

9. The method of claim 1, wherein the first layer comprises gallium nitride (GaN) and the second layer comprises aluminum gallium nitride (AlGaN), and wherein the buffer layer comprises aluminum nitride and alternating layers of GaN and AlGaN.

10. The method of claim 1, wherein the substrate layer comprises silicon, wherein the silicon in the substrate layer has a resistivity that does not exceed one milliohm-centimeter.

11. The method of claim 1, wherein the opening is aligned with the gate contact.