SEMICONDUCTOR STRUCTURES INCLUDING LINERS COMPRISING ALUCONE AND RELATED METHODS

• US 20190312200A1
• Filed: 06/20/2019
• Published: 10/10/2019
• Est. Priority Date: 02/25/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Song, Zhe, Allen, Tuman E., Franklin, Cole S., Gealy, F. Daniel
• Granted Patent: US 11,223,014 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02118 carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC polymers per se C08G, photoresist per se G03F
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02362 formation of intermediate layers, e.g. capping layers or diffusion barriers
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/24 of the Ovonic threshold switching type
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/021 Formation of the switching material, e.g. layer deposition
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/068 by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/235 between different crystalline phases, e.g. cubic and hexagonal
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/882 : Compounds of sulfur, selenium or tellurium, e.g. chalcogenides

Abstract

A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.

Claims

1. A semiconductor device, comprising:

stack structures adjacent a material; and

a liner adjacent the stack structures, the liner comprising a first portion comprising aluminum oxide in contact with the stack structures and a second portion comprising alucone adjacent the first portion.

2. The semiconductor device of claim 1, wherein the liner comprises a gradient of alucone and aluminum oxide.

3. The semiconductor device of claim 1, wherein the second portion further comprises silicon atoms, nitrogen atoms, or a combination thereof.

4. The semiconductor device of claim 1, wherein the liner comprises a ratio of aluminum oxide to alucone of from about 1:

1 to about 1;

10.

5. The semiconductor device of claim 1, wherein the stack structures comprise an electrode material and a switching material adjacent the electrode.

6. The semiconductor device of claim 1, wherein the liner further comprises a third portion between the first portion and the second portion, the third portion comprising a greater amount of alucone than the first portion.

7. The semiconductor device of claim 1, wherein the stack structures comprise an electrode material between a switching material and a phase change material.

8. The semiconductor device of claim 1, wherein the liner has a thickness ranging from about 5 Å

to about 30 Å

.

9. The semiconductor device of claim 1, wherein the stack structures comprise alternating conductive materials and dielectric materials.

10. A semiconductor device, comprising:

stack structures comprising alternating dielectric materials and conductive materials adjacent a base material; and

a liner comprising alucone adjacent at least a portion of the stack structures.

11. The semiconductor device of claim 10, wherein the stack structures comprises a control gate material.

12. The semiconductor device of claim 10, wherein the liner comprises a first portion comprising aluminum oxide contacting sidewalls of the stack structures and a second portion comprising alucone over the first portion.

13. The semiconductor device of claim 10, wherein the liner has a thickness between about 5 Å

and about 30 Å

.

14. The semiconductor device of claim 10, further comprising a charge trap adjacent the liner.

15. The semiconductor device of claim 14, wherein the charge trap comprises a charge trapping material between a tunnel dielectric material and a charge blocking material.

16. The semiconductor device of claim 14, wherein the charge trap comprises an oxide-nitride-oxide material.

17. The semiconductor device of claim 10, wherein the liner comprises a gradient of alucone, a concentration of alucone increasing from about zero percent at a portion of the liner proximal the stack structures to about one-hundred percent at a portion of the liner distal from the stack structures.

18. A method of forming a semiconductor device, the method comprising:

forming stack structures adjacent a base material;

forming aluminum oxide adjacent to and in contact with the stack structures; and

forming alucone adjacent to the aluminum oxide.

19. The method of claim 18, wherein forming alucone adjacent to the aluminum oxide comprises forming the alucone to exhibit a gradient of alucone and aluminum oxide.

20. The method of claim 18, wherein forming stack structures adjacent a base material comprises forming stack structures comprising alternating dielectric materials and conductive materials adjacent a base material.