MAGNETIC SENSING SCHEME FOR VOLTAGE REGULATOR CIRCUIT

• US 20190312513A1
• Filed: 06/25/2019
• Published: 10/10/2019
• Est. Priority Date: 06/25/2019
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jain, Amit Kumar, Kuan, Chin Lee, Shekhar, Sameer
• Granted Patent: US 11,502,603 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 19/16504 characterised by the components employed
• CPC Class Codes: G01R 19/16576 comparing DC or AC voltage with one threshold G01R19/16514, G01R19/16519, G01R19/16528, G01R19/16533 and G01R19/1659 take precedence
• CPC Class Codes: G01R 33/0283 in which a current or voltage is generated due to relative movement of conductor and magnetic field
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H01F 27/28 Coils; Windings; Conductive connections
• CPC Class Codes: H01F 27/402 Association of measuring or protective means
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 1/0064 Magnetic structures combining different functions, e.g. storage, filtering or transformation
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load

Abstract

Various embodiments provide a magnetic sensing scheme for a voltage regulator circuit. The voltage regulator circuit may include a first inductor (also referred to as an output inductor) coupled between a drive circuit and an output node. The voltage regulator circuit may further include a second inductor (also referred to as a sense inductor) having a first terminal coupled to the first inductor at a tap point between terminals of the first inductor. The second inductor may provide a sense voltage at a second terminal of the second inductor. A control circuit may control a state of the voltage regulator circuit based on the sense voltage to provide a regulated output voltage at the output node. Other embodiments may be described and claimed.

Claims

1. A voltage regulator circuit comprising:

a pull-up transistor coupled between an intermediate node and a supply rail that is to receive an input voltage;

a pull-down transistor coupled between the intermediate node and a ground terminal;

a first inductor coupled between the intermediate node and an output node to provide a regulated output voltage at the output node;

a second inductor having a first terminal coupled to the first inductor at a tap point between terminals of the first inductor, wherein the second inductor is magnetically coupled to the first inductor, and wherein the second inductor is to provide a sense voltage at a second terminal of the second inductor; and

a control circuit to receive the sense voltage and to control the pull-up transistor and the pull-down transistor based on the sense voltage.

2. The voltage regulator circuit of claim 1, wherein the control circuit includes:

a comparator to compare the sense voltage to a reference voltage; and

a driver circuit to control the pull-up transistor and the pull-down transistor based on the comparison.

3. The voltage regulator circuit of claim 2, wherein the control circuit is to:

turn on the pull-up transistor and turn off the pull-down transistor if the sense voltage is less than the reference voltage; and

turn off the pull-up transistor and turn on the pull-down transistor if the sense voltage is greater than the reference voltage.

4. The voltage regulator circuit of claim 1, wherein the sense voltage is based on a current through the first inductor, the input voltage, and the regulated output voltage.

5. The voltage regulator circuit of claim 1, wherein, when the pull-up transistor is on and the pull-down transistor is off, the sense voltage has a value according to:

V_SENSE=K₁I_{L_AC}+(1−

K₂)V_OUT+K₂V_IN

wherein V_SENSE is the sense voltage, I_{L_AC} is an alternating current (AC) through the first inductor, V_OUT is the output voltage, V_IN is the input voltage, K₁ is a transformation ratio of the second inductor compared with the first inductor, and K₂ is an inductance ratio between a portion of the first inductor from the tap point to the output node compared with the first inductor in total.

6. The voltage regulator circuit of claim 5, wherein, when the pull-up transistor is off and the pull-down transistor is on, the sense voltage has a value according to:

V_SENSE=K₁I_{L_AC}+(1−

K₂)V_OUT.

7. The voltage regulator circuit of claim 5, wherein K₁ has a value according to:

8. The voltage regulator circuit of claim 1, wherein the first and second inductors are spiral wound inductors.

9. The voltage regulator circuit of claim 1, wherein the first and second inductors are toroidal inductors.

10. The voltage regulator circuit of claim 1, wherein the first and second inductors are coaxial inductors having respective straight conductors embedded in a magnetic material.

11. A circuit comprising:

an output stage to receive an input voltage and provide a regulated output voltage at an output node, the output stage including an inductor;

a feedback circuit to provide a feedback signal based on an inductor current through the inductor, an input voltage, and the regulated output voltage; and

a control circuit to control operation of the output stage based on the feedback signal.

12. The circuit of claim 11, wherein the inductor is coupled between the output node and an intermediate node of the output stage, and wherein the output stage further includes:

a pull-up transistor coupled between the intermediate node and an input terminal that is to receive the input voltage; and

a pull-down transistor coupled between the intermediate node and a ground terminal.

13. The circuit of claim 12, wherein the control circuit is to:

turn on the pull-up transistor and turn off the pull-down transistor if the sense voltage is less than a first voltage threshold; and

turn off the pull-up transistor and turn on the pull-down transistor if the sense voltage is greater than a second voltage threshold.

14. The circuit of claim 12, wherein the second voltage threshold is the same as the first voltage threshold.

15. The circuit of claim 11, wherein the inductor is a first inductor, and wherein the feedback circuit includes a second inductor with a first terminal coupled to the first inductor at a tap point between terminals of the first inductor, wherein the second inductor is to provide the feedback signal at a second terminal of the second inductor.

16. The circuit of claim 15, wherein the output stage is controllable by the control circuit to be in a charge state in which the inductor current is to increase and a discharge state in which the inductor current is to decrease, and wherein, when the output stage is in the charge state, the sense voltage has a value according to:

V_SENSE=K₁I_{L_AC}+(1−

K₂)V_OUT+K₂V_IN

wherein V_SENSE is the sense voltage, I_{L_AC} is an alternating current (AC) component of the inductor current, V_OUT is the output voltage, V_IN is the input voltage, K₁ is a transformation ratio of the second inductor compared with the first inductor, and K₂ is an inductance ratio between a portion of the first inductor from the tap point to the output node compared with the first inductor in total.

17. The circuit of claim 16, wherein, when the output stage is in the discharge state, the sense voltage has a value according to:

V_SENSE=K₁I_{L_AC}+(1−

K₂)V_OUT.

18. The circuit of claim 16, wherein K₁ has a value according to:

19. A computing system comprising:

a motherboard; and

an integrated circuit die mounted to the motherboard, the integrated circuit die comprising;

a circuit block; and

a voltage regulator to provide a regulated output voltage to the circuit block at an output node, wherein the voltage regulator is operable in a charge mode and a discharge mode, and wherein the voltage regulator includes;

a first inductor coupled to the output node;

a second inductor having a first terminal coupled to the first inductor at a tap point between terminals of the first inductor, wherein the second inductor is magnetically coupled to the first inductor, and wherein the second inductor is to provide a sense voltage at a second terminal of the second inductor; and

a control circuit to receive the sense voltage and to switch the voltage regulator between the charge mode and the discharge mode based on the sense voltage.

20. The computing system of claim 19, wherein the inductor is coupled between the output node and an intermediate node, and wherein the voltage regulator further includes:

a pull-up transistor coupled between the intermediate node and an input terminal that is to receive an input voltage; and

a pull-down transistor coupled between the intermediate node and a ground terminal;

wherein, when the voltage regulator is in the charge state, the pull-up transistor is to be on and the pull-down transistor is to be off; and

wherein, when the voltage regulator is in the discharge state, the pull-up transistor is to be off and the pull-down transistor is to be on.

21. The computing system of claim 19, wherein the control circuit is to:

switch the voltage regulator from the discharge state to the charge state based on a first detection that the sense voltage is less than a reference voltage; and

switch the voltage regulator from the charge state to the discharge state based on a second detection that the sense voltage is greater than the reference voltage.

22. The computing system of claim 19, wherein the sense voltage is based on a current through the first inductor, an input voltage to be received by the voltage regulator, and the regulated output voltage.

23. The computing system of claim 19, wherein, when the voltage regulator is in the charge state, the sense voltage has a value according to:

V_SENSE=K₁I_{L_AC}+(1−

K₂)V_OUTK₂V_IN

wherein V_SENSE is the sense voltage, I_{L_AC} is an alternating current (AC) through the first inductor, V_OUT is the output voltage, V_IN is an input voltage to be received by the voltage regulator, K₁ is a transformation ratio of the second inductor compared with the first inductor, and K₂ is an inductance ratio between a portion of the first inductor from the tap point to the output node compared with the first inductor in total.

24. The computing system of claim 23, wherein, when the voltage regulator is in the discharge state, the sense voltage has a value according to:

V_SENSE=K₁I_{L_AC}+(1−

K₂)V_OUT.

25. The computing system of claim 19, further comprising one or more of a memory circuit, a display, or an antenna coupled to the integrated circuit die.