RECEIVER CIRCUIT

• US 20190312550A1
• Filed: 04/04/2018
• Published: 10/10/2019
• Est. Priority Date: 04/04/2018
• Status: Active Grant

• Current Assignee: Northeastern University, SK Hynix Inc.
• Original Assignee: Northeastern University, SK Hynix Inc.
• Inventors: JUNG, Hae Kang, CHOI, Yong Suk, KIM, Yong Bin, JEON, Gyunam, KWON, Dae-Han, CHO, Joo Hwan
• Granted Patent: US 10,734,951 B2
• Time in Patent Office: Days
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 2200/129 there being a feedback over the complete amplifier
• CPC Class Codes: H03F 2200/87 the cross coupling circuit being realised only by MOSFETs
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages
• CPC Class Codes: H03G 3/002 Control of digital or coded signals H03G3/3089 take precedence
• CPC Class Codes: H03G 3/3036 in high-frequency amplifiers or in frequency-changers H03G3/3052, H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03G 3/3052 in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03K 19/0027 in field effect transistor circuits
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H03K 3/356 Bistable circuits
• CPC Class Codes: H03K 3/35613 the input circuit having a differential configuration
• CPC Class Codes: H03K 3/356182 with additional means for controlling the main nodes
• CPC Class Codes: H04B 1/16 Circuits

Abstract

A receiver circuit receives a signal from a semiconductor device. The receiver circuit includes an input buffer including a first plurality of transistors, the input buffer being configured to detect a fabrication condition of the receiver circuit, generate a control signal according to the detected fabrication condition, and control a gain of an input signal by adjusting a number of operating transistors among the first plurality of transistors in response to the control signal; and a latch circuit configured to latch an output signal of the input buffer, and adjust threshold voltages of a second plurality of transistors in response to a test signal.

Claims

1. A receiver circuit comprising:

an input buffer including a first plurality of transistors, the input buffer being configured to detect a fabrication condition of the receiver circuit by a fabrication sensor, generate a control signal according to the detected fabrication condition, and control a gain of an input signal by adjusting a number of operating transistors among the first plurality of transistors in response to the control signal; and

a latch circuit configured to latch an output signal of the input buffer and adjust threshold voltages of a second plurality of transistors in response to a test signal.

2. The receiver circuit according to claim 1, wherein the input buffer includes:

the fabrication sensor configured to output a sensing signal by detecting the fabrication condition;

an analog-to-digital converter (ADC) configured to generate the control signal by converting the sensing signal into the control signal;

a controller configured to generate a gain controlled signal in response to a mode signal and the control signal; and

an amplification circuit configured to amplify the input signal according to the gain by changing the number of the operating transistors according to the gain controlled signal of the controller.

3. The receiver circuit according to claim 2, wherein the fabrication sensor stops sensing after being operated only once.

4. The receiver circuit according to claim 2, wherein the controller is a first gain controller, the receiver circuit further comprising a second gain controller.

5. The receiver circuit according to claim 4, wherein each of the first and second gain controllers includes:

a selection circuit configured to output first and second selection signals in response to the control signal and the mode signal; and

an output circuit configured to transmit or block the input signal in response to the first selection signal or the second selection signal.

6. The receiver circuit according to claim 5, wherein each of the first and second gain controllers further includes:

a precharge circuit configured to precharge an output terminal in response to the first selection signal or the second selection signal.

7. The receiver circuit according to claim 5, wherein:

when the mode signal indicates a first mode, the selection circuit changes one or both of a logic value of the first selection signal and a logic value of the second selection signals in response to the control signal; and

when the mode signal indicates a second mode, the selection circuit maintains the logic values of the first and second selection signals at a specific value.

8. The receiver circuit according to claim 5, wherein:

when the control signal indicates a slow fabrication condition, the selection circuit generates the first and second selection signals both having a logic high value;

when the control signal indicates a typical fabrication condition, the selection circuit generates the first selection signal having a logic low value and generates the second selection signal having a logic high value; and

when the control signal indicates a fast fabrication condition, the selection circuit generates the first selection signal having the logic high value and generates the second selection signal having the logic low value.

9. The receiver circuit according to claim 2, wherein the controller is one of a first gain controller, a second gain controller, and a third gain controller,

wherein the first gain controller is configured to output a plurality of data signals as the gain controlled signal in response to the mode signal, the input signal, and the control signal,

wherein the second gain controller is configured to output a plurality of gate control signals as the gain controlled signal, in response to the mode signal, a clock signal, and the control signal, and

wherein a third gain controller is configured to output a plurality of reference signals as the gain controlled signal in response to the mode signal, an inverted version of the input signal, and the control signal.

10. The receiver circuit according to claim 2, wherein the gain controlled signal is one of a data signal, a gate control signal, and a reference signal,

wherein the amplification circuit includes:

a first transistor array including a plurality of tail transistors, each of the plurality of tail transistors being configured to pull up a first node by a corresponding signal of the gate controlled signal, a number of operating tail transistors varying in response to the gate control signal; and

a second transistor array including a plurality of input transistors, each of the plurality of input transistors being coupled to the first node, a number of operating input transistors varying in response to the data signal or the reference signal.

11. The receiver circuit according to claim 10, wherein the plurality of tail transistors have different driving capabilities, and the plurality of input transistors have different driving capabilities.

12. The receiver circuit according to claim 2, wherein, when the mode signal indicates a first mode, the number of the operating transistors is the same as a number of the first plurality of transistors of the input buffer.

13. The receiver circuit according to claim 2, wherein, when the mode signal indicates a second mode, the number of the operating transistors is less than a number of the first plurality of transistors of the input buffer.

14. The receiver circuit according to claim 2, wherein the mode signal indicates one of a high-performance mode and a low-power mode.

15. The receiver circuit according to claim 1, wherein the latch circuit includes:

a data latch configured to latch the output signal of the input buffer;

an inversion circuit configured to invert the output signal of the input buffer;

a ladder circuit configured to adjust a resistance value in response to a plurality of switching signals, and provide a signal corresponding to the adjusted resistance value to the inversion circuit; and

a switching signal generation circuit configured to generate the plurality of switching signals in response to the test signal.

16. The receiver circuit according to claim 15, wherein the data latch is an SR latch.

17. The receiver circuit according to claim 15, wherein the inversion circuit includes a transistor, a bulk voltage of the transistor being controlled in response to the signal corresponding to the adjusted resistance value of the ladder circuit.

18. The receiver circuit according to claim 15, wherein the ladder circuit controls a threshold voltage of a pull-down transistor of the inversion circuit in response to the plurality of switching signals.

19. The receiver circuit according to claim 15, wherein the ladder circuit includes:

a plurality of resistors coupled in series between a power-supply voltage terminal and a ground; and

a plurality of switching circuits each having a first end coupled to a bulk terminal of a transistor in the inversion circuit and having a second end coupled to a connection node between two neighboring ones of the plurality of resistors, each of the switching circuits being turned on in response to a corresponding one of the plurality of switching signals.

20. The receiver circuit according to claim 15, wherein the switching signal generation circuit generates the plurality of switching signals during a training mode of a semiconductor device, the semiconductor device including the receiver circuit.