DIGITALLY CONTROLLABLE OSCILLATOR WITH HIGH ACCURACY

• US 20190312581A1
• Filed: 04/19/2019
• Published: 10/10/2019
• Est. Priority Date: 10/20/2016
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: LAMANNA, Pasquale, CARDISCIANI, Danilo
• Granted Patent: US 10,979,060 B2
• Time in Patent Office: Days
• CPC Class Codes: H03B 5/12 active element in amplifier being semiconductor device H03B5/14 takes precedence
• CPC Class Codes: H03B 5/1212 the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
• CPC Class Codes: H03B 5/1265 switched capacitors
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/0991 the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814
• CPC Class Codes: H03L 7/0993 and a circuit for adding and deleting pulses
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

An oscillator is provided. The oscillator is configured for generating an output signal which is phase locked to an input signal. The oscillator comprises a controlled oscillator configured for generating the output signal based on an oscillator input signal. Moreover, the oscillator comprises a frequency divider configured for dividing the frequency of the output signal, resulting in a frequency divided feedback signal. Also, the oscillator comprises a phase detector, which is configured for generating an error signal based upon the frequency divided feedback signal and the input signal. Also, the oscillator comprises an error signal pulse train modulator configured for generating the oscillator input signal by performing a pulse train modulation of the error signal) or a signal derived from the error signal based on the input signal.

Claims

1. An oscillator, comprising:

a controlled oscillator configured to generate an output signal based on an oscillator input signal;

a frequency divider configured for to divide the a frequency of the output signal to generate a frequency divided feedback signal;

a phase detector configured to generate an error signal based upon the frequency divided feedback signal and an input signal; and

an error signal pulse train modulator configured to generate the oscillator input signal by being configured to perform a pulse train modulation of the error signal or a signal derived from the error signal based on the input signal,

wherein the output signal is phase locked to the input signal.

2. The oscillator of claim 1,

wherein the oscillator further comprises a loop filter configured to low-pass filter the error signal to generate a filtered error signal, and

wherein the error signal pulse train modulator is configured to generate the oscillator input signal by being configured to perform a pulse train modulation of the filtered error signal.

3. The oscillator of claim 1,

wherein the oscillator input signal comprises a number x of pulses separated by a number N−

x of gaps within the a period of the input signal,

wherein N is a number of slots for pulses and gaps within the period of the input signal, and

wherein the number x of pulses is proportional to the error signal or the signal derived from the error signal.

4. The oscillator of claim 3, wherein the error signal pulse train modulator is further configured to:

equally space the x number of pulses over the period of the input signal, and

equally space the N−

x gaps over the period of the input signal.

5. The oscillator of claim 3, wherein the error signal pulse train modulator is further configured to:

set an equal first time duration for all pulses, and

set an equal second time duration for all gaps.

6. The oscillator of claim 1,

wherein the error signal pulse train modulator comprises an input signal modulator configured to generate a number N of modulator output signals, wherein

a number x of the N modulator output signals is at a high state,

wherein a number (N−

x) of the modulator output signals is at a low state,

wherein x/N is proportional to the error signal or the signal derived from the error signal,

and

wherein the error signal pulse train modulator is further configured to generate the oscillator input signal from x/N.

7. The oscillator of claim 6,

wherein the error signal pulse train modulator further comprises a flip-flop chain,

wherein the flip-flop chain comprises N flip-flops,

wherein the input signal is supplied to an enable input of a first flip-flop in the flip-flop chain, and

wherein the N flip-flops of the flip-flop chain are arranged so that an inverted output of each flip-flop is connected to an enable input of a following flip-flop in the flip-flop chain.

8. The oscillator of claim 6,

wherein the error signal pulse train modulator further comprises a first flip-flop chain and a second flip-flop chain,

wherein the first flip-flop chain comprises N/2 flip-flops,

wherein the second flip-flop chain comprises N/2 flip-flops,

wherein the input signal is supplied to an enable input of a first flip-flop in the first flip-flop chain and to a first flip-flop in the second flip-flop chain,

wherein the N/2 flip-flops of the first flip-flop chain are arranged so that an inverted output of each flip-flop is connected to an enable input of a following flip-flop in the first flip-flop chain,

wherein the N/2 flip-flops of the second flip-flop chain are arranged so that an inverted output of each flip-flop is connected to an enable input of a following flip-flop in the second flip-flop chain,

wherein the first flip-flop chain is active during a high period of the input signal, and

wherein the second flip-flop chain is active during a low period of the input signal.

9. The oscillator of claim 7,

wherein the error signal pulse train modulator further comprises a weighting unit configured to

weigh the output of each flip-flop with one of the N modulator output signals to generate N weighted flip-flop output signals.

10. The oscillator of claim 9,

wherein the weighting unit is further configured to add the N weighted flip-flop output signals to generate the oscillator input signal.

11. The oscillator of claim 7,

wherein clock inputs of the N flip-flops are supplied with a clock signal derived from the output signal.

12. The oscillator of claim 11,

wherein the frequency divider comprises:

a first frequency divider configured to divide the frequency of the output signal to generate a first frequency divided signal; and

a second frequency divider configured to divide a frequency of the first frequency divided signal to generate the frequency divided feedback signal, and

wherein the first frequency divided signal is the clock signal.

13. The oscillator of claim 1,

wherein the input signal, the output signal, the oscillator input signal, the frequency divided feedback signal, the error signal, and the signal derived from the error signal are digital signals, and

wherein the controllable oscillator is a digitally controllable oscillator.

14. The oscillator of claim 1,

wherein a frequency of the input signal is at least by a factor of 10 lower than the frequency of the output signal.

15. A method for generating an output signal, comprising:

generating, by a controlled oscillator, the output signal based on an oscillator input signal;

dividing, by a frequency divider, a frequency of the output signal to generate a frequency divided feedback signal;

generating, by a phase detector, an error signal based upon the frequency divided feedback signal and an input signal; and

generating, by an error signal pulse train modulator, the oscillator input signal by performing a pulse train modulation of the error signal or a signal derived from the error signal based on the input signal,

wherein the output signal is phase locked to the input signal.

16. The method of claim 15, further comprising:

low-pass filtering, by a loop filter, the error signal to generate a filtered error signal, and

wherein generating by the error signal pulse train modulator the oscillator input signal comprises performing a pulse train modulation of the filtered error signal.

17. The method of claim 15,

wherein the oscillator input signal comprises a number x of pulses separated by a number (N−

x) of gaps within a period of the input signal,

wherein N is a number of slots for pulses and gaps within the period of the input signal, and

wherein the number x of pulses is proportional to the error signal or the signal derived from the error signal.

18. The method of claim 17, further comprising:

spacing equally, by the error signal pulse train modulator, the x number of pulses over the period of the input signal; and

spacing equally, by the error signal pulse train modulator, the (N−

x) gaps over the period of the input signal.

19. The method of claim 17, further comprising:

setting, by the error signal pulse train modulator, an equal first time duration for all pulses, and

setting, by the error signal pulse train modulator, an equal second time duration for all gaps.

20. The method of claim 15, further comprising:

generating, by the error signal pulse train modulator, a number N of modulator output signals, wherein a number x of the N modulator output signals is at a high state, a number (N−

x) of the modulator output signals is at a low state, wherein x/N is proportional to the error signal or the signal derived from the error signal, and

generating, by the error signal pulse train modulator, the oscillator input signal from x/N.