RETRANSMISSION SCHEME FOR LOWDENSITY PARITY CHECK CODING

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First Claim
1. A method comprising:
 encoding, by a first apparatus, a data bit set by using a first parity check matrix in a lowdensity parity check encoder, thus providing a first parity bit set;
causing, by the first apparatus, transmission of the data bit set and at least some parity bits of the first parity bit set to a second apparatus in a message;
determining, by the first apparatus, that the second apparatus was not capable of decoding the data bit set;
modifying, by the first apparatus, the first parity check matrix by using an overlapping matrix such that overlapping elements of the first parity check matrix and the overlapping matrix are combined, thus acquiring a second parity check matrix;
encoding, by the first apparatus, the data bit set by using the second parity check matrix in the lowdensity parity check encoder, thus providing a second parity bit set; and
causing transmission of at least some parity bits of the second parity bit set to the second apparatus.
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Abstract
This document discloses a solution for using lowdensity parity check codes in connection with a retransmission scheme in a wireless network. According to an aspect a method comprises: encoding, by a first apparatus, a data bit set by using a first parity check matrix in a lowdensity parity check encoder, thus providing a first parity bit set; causing, by the first apparatus, transmission of the data bit set and at least some parity bits of the first parity bit set to a second apparatus in a message; determining, by the first apparatus, that the second apparatus was not capable of decoding the data bit set; modifying, by the first apparatus, the first parity check matrix by using an overlapping matrix such that overlapping elements of the first parity check matrix and the overlapping matrix are combined, thus acquiring a second parity check matrix; encoding, by the first apparatus, the data bit set by using the second parity check matrix in the lowdensity parity check encoder, thus providing a second parity bit set; and causing transmission of at least some parity bits of the second parity bit set to the second apparatus.
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33 Claims
 1. A method comprising:
encoding, by a first apparatus, a data bit set by using a first parity check matrix in a lowdensity parity check encoder, thus providing a first parity bit set; causing, by the first apparatus, transmission of the data bit set and at least some parity bits of the first parity bit set to a second apparatus in a message; determining, by the first apparatus, that the second apparatus was not capable of decoding the data bit set; modifying, by the first apparatus, the first parity check matrix by using an overlapping matrix such that overlapping elements of the first parity check matrix and the overlapping matrix are combined, thus acquiring a second parity check matrix; encoding, by the first apparatus, the data bit set by using the second parity check matrix in the lowdensity parity check encoder, thus providing a second parity bit set; and causing transmission of at least some parity bits of the second parity bit set to the second apparatus.  View Dependent Claims (2, 3, 7)
 46. 6. (canceled)
 816. 16. (canceled)
 17. An apparatus comprising:
at least one processor, and at least one memory comprising a computer program code, wherein the processor, the memory, and the computer program code are configured to cause the apparatus to; encode a data bit set by using a first parity check matrix in a lowdensity parity check encoder, thus providing a first parity bit set; cause transmission of the data bit set and at least some parity bits of the first parity bit set to a second apparatus in a message; determine that the second apparatus was not capable of decoding the data bit set; modify the first parity check matrix by using an overlapping matrix such that overlapping elements of the first parity check matrix and the overlapping matrix are combined, thus acquiring a second parity check matrix; encode the data bit set by using the second parity check matrix in the lowdensity parity check encoder, thus providing a second parity bit set; and cause transmission of at least some parity bits of the second parity bit set to the second apparatus.  View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
 25. An apparatus comprising:
at least one processor, and at least one memory comprising a computer program code, wherein the processor, the memory, and the computer program code are configured to cause the apparatus to; receive, from a second apparatus, a first message comprising a data bit set and a first parity bit set; decode, in a lowdensity parity check decoder, the data bit set by using the first parity bit set and a first parity check matrix known to be used for encoding the data bit set in the second apparatus; determine that the lowdensity parity check decoder was not capable of decoding the data bit set; receive, from the second apparatus, a second message comprising a second parity bit set different from the first parity bit set; modify the first parity check matrix by using an overlapping matrix such that overlapping elements of the first parity check matrix and the overlapping matrix are combined, thus acquiring a second parity check matrix; decode, in the lowdensity parity check decoder, the data bit set by using at least the second parity bit set and the second parity check matrix.  View Dependent Claims (26, 27, 28, 29, 30, 31, 32)
 3335. 35. (canceled)
1 Specification
The invention relates to a solution for carrying out retransmissions in a wireless system employing lowdensity parity check channel coding.
LowDensity Parity Check (LDPC) codes have been used in wireless systems. LDPC codes as such are well known in coding theory and known to approach the Shannon channel capacity limit when utilized properly in data transmission. Irregular LDPC codes are known from the fact that input bits may be encoded with different degrees of coding strength, i.e. each input bit may be protected by a different number of parity check equations. Regular LDPC codes employ the same number of parity check equations for each systematic bit.
An LDPC code can be represented by a bipartite graph, which consists of variable nodes, check nodes and a certain number of edges between these two types of node. Each variable node represents a bit of the codeword and each check nodes represents a parity check of the code. An edge exist between a variable node and a check node only if this bit is checked by this edgeconnected parity check equation. The degree of a node is the number of edges connected to this node. An irregular LDPC code has a bipartite graph in which the bit nodes (check nodes) have different degrees. A higher variable node degree means that a bit is protected by more parity check equations, which implies to a lower bit error probability. In this manner, a parity check matrix may be constructed. The parity check matrix defines how parity check bits should be calculated. That is, each parity check bit is calculated from given one or more systematic data bits and parity bits.
Quasicyclic LDPC (QCLDPC) codes have been designed to provide efficient implementations. In a quasicyclic implementation, the parity check matrix is constructed by a plurality of submatrices, wherein at least some of the submatrices are circulant permutation matrices. Some of the other submatrices may have another constructions, e.g. a zero matrix construction.
A publication by Beomkyu Shin et al: “Quasicyclic LDPC Codes Using Overlapping Matrices and Their Layered Decoders”, International Journal of Electronics and Communications, VOL. 68(5), 2014 discloses a method for using QCLDPC codes and a decoder structure for QCLDPC codes when the system employs multiple parity check matrices.
The invention is defined by the subjectmatter of the independent claims. Embodiments are defined in the dependent claims.
In the following, the invention will be described in greater detail with reference to the embodiments and the accompanying drawings, in which
The following embodiments are exemplifying. Although the specification may refer to “an”, “one”, or “some” embodiment(s) in several locations of the text, this does not necessarily mean that each reference is made to the same embodiment(s), or that a particular feature only applies to a single embodiment. Single features of different embodiments may also be combined to provide other embodiments.
Embodiments described may be implemented in a radio system, such as in at least one of the following: Universal Mobile Telecommunication System (UMTS, 3G) based on basic widebandcode division multiple access (WCDMA), highspeed packet access (HSPA), Long Term Evolution (LTE), LTEAdvanced, a system based on IEEE 802.11 specifications, a system based on IEEE 802.15 specifications, and/or a fifth generation (5G) mobile or cellular communication system.
The embodiments are not, however, restricted to the system given as an example but a person skilled in the art may apply the solution to other communication systems provided with necessary properties. One example of a suitable communications system is the 5G system, as listed above. 5G has been envisaged to use multipleinputmultipleoutput (MIMO) multiantenna transmission techniques, more base stations or nodes than the current network deployments of LTE, by using a socalled small cell concept including macro sites operating in cooperation with smaller local area access nodes and perhaps also employing a variety of radio technologies for better coverage and enhanced data rates. 5G will likely be comprised of more than one radio access technology (RAT), each optimized for certain use cases and/or spectrum. 5G system may also incorporate both cellular (3GPP) and noncellular (e.g. IEEE) technologies. 5G mobile communications will have a wider range of use cases and related applications including video streaming, augmented reality, different ways of data sharing and various forms of machine type applications, including vehicular safety, different sensors and realtime control. 5G is expected to have multiple radio interfaces, including apart from earlier deployed frequencies below 6 GHz, also higher, that is cmWave and mmWave frequencies, and also being integratable with existing legacy radio access technologies, such as the LTE. Integration with the LTE may be implemented, at least in the early phase, as a system, where macro coverage is provided by the LTE and 5G radio interface access comes from small cells by aggregation to the LTE. In other words, 5G is planned to support both interRAT operability (such as LTE5G) and interRI operability (interradio interface operability, such as interRI operability between cmWave and mmWave). One of the concepts considered to be used in 5G networks is network slicing in which multiple independent and dedicated virtual subnetworks (network instances) may be created within the same infrastructure to run services that have different requirements on latency, reliability, throughput and mobility.
It should be appreciated that future networks will most probably utilize network functions virtualization (NFV) which is a network architecture concept that proposes virtualizing network node functions into “building blocks” or entities that may be operationally connected or linked together to provide services. A virtualized network function (VNF) may comprise one or more virtual machines running computer program codes using standard or general type servers instead of customized hardware. Cloud computing or cloud data storage may also be utilized. In radio communications this may mean node operations to be carried out, at least partly, in a server, host or node operationally coupled to a remote radio head. It is also possible that node operations will be distributed among a plurality of servers, nodes or hosts. It should also be understood that the distribution of labour between core network operations and base station operations may differ from that of the LTE or even be nonexistent. Some other technology advancements probably to be used are SoftwareDefined Networking (SDN), Big Data, and allIP, which may change the way networks are being constructed and managed.
In the case of multiple access nodes in the communication network, the access nodes may be connected to each other with an interface. LTE specifications call such an interface as X2 interface. In IEEE 802.11 networks, a similar interface may be provided between access points. Other wired or wireless communication methods between the access nodes may also be possible. The access nodes may be further connected via another interface to a core network 130 of the cellular communication system. The LTE specifications specify the core network as an evolved packet core (EPC), and the core network may comprise a mobility management entity (MME) 132 and a gateway (GW) node 134. The MME may handle mobility of terminal devices in a tracking area encompassing a plurality of cells and also handle signalling connections between the terminal devices and the core network 130. The gateway node 134 may handle data routing in the core network 130 and to/from the terminal devices. In some scenarios, the different access nodes may be connected to different core networks. The different core networks may be operated by the same operator or by different operators.
The radio system of
Channel encoding is commonly in wireless communication links to combat signal degradation in a radio channel. The channel encoding is typically based on processing data bits in a channel encoder and outputting encoded data bits to further processing in a radio transmitter. The channel encoder typically outputs bits at a higher data rate than a data rate at its input. In other words, the channel encoder computes additional information from the data bits. A systematic channel coding scheme maintains the original data bits at its output and, additionally, outputs parity bits that may be used as additional information in a channel decoder. The lowdensity parity check (LDPC) codes described in the Background section are an example of such channel codes. In many wireless links, an automatic repeat request (ARQ) scheme is also used for retransmissions related to data not being successfully decoded in a receiver. The ARQ scheme is based on the receiver acknowledging (ACK) successful decoding of the data to the transmitter. Some systems employ also negative acknowledgments (NACK/NAK) for the receiver to indicate the failed decoding of the data. Other systems do not employ the NACK/NAK. In such systems, upon not receiving the ACK within a determined time window from the transmission, the transmitter carries out a retransmission.
Embodiments of the present invention employ the LDPC channel codes in connection with an ARQ process. The ARQ process used in the described embodiments is a hybrid ARQ process where the transmitter may transmit different information in an initial transmission and in retransmission.
Referring to
In an embodiment, the combining is carried out by using one of the following combining methods: a sum, a modulo2 sum, a logical binary OR operation, or a logical binary exclusive OR (XOR) operation. Other solutions for carrying out a function where a similar combining effect is realized may equally be used. For example, any rule that combines values ‘0’ and ‘1’ to value ‘1’ and values ‘0’ and ‘0’ to a value ‘0’ may be used. The first parity check matrix and the overlapping matrix may be designed so that no combining of values ‘1’ and ‘1’ is needed because a purpose may be to have more values ‘1’ in the second parity check matrix than in the first parity check matrix (see description below).
Referring to
As described above, the parity check matrix is recomputed after the initial transmission, and parity bits acquired from the recomputed parity check matrix are transmitted in the retransmission. Such additional processing of the parity check matrix may improve the decoding performance compared with a scheme where only parity bits of the initial parity check matrix are used in the retransmission. Let us now describe the encoding and decoding in connection with the HARQ process in greater detail with reference to
Referring to
Each “box” in Table 1 may represent a submatrix called a protograph matrix of size W*W. Accordingly, the initial parity check matrix 404 in this example consists of 6 W rows and 24 W columns. Some of the protograph matrices may be identity matrices wherein elements of the matrix are cyclically shifted according to the number indicated in Table 1. For example, number 1 may indicate that values of the identity matrix are cyclically shifted by one element, thus resulting in the following matrix representation (assuming W=3):
Consequently, the cyclic shift may be understood as shifting the values along each row in a cyclic manner such that the last value on a row is shifted to the beginning of the row. In this case, the cyclic shft is to the right but it could equally be to the left. This is an overly simplified example with a small value of W and, in real implementations, W may be much higher. W may depend on the design of the encoder but, in any case, it may be higher than the highest value in the boxes of Table 1. Protograph matrices in Table 1 having value “0” (zero) may be identity matrices of size (W, W) with no cyclic shift. Protograph matrices in Table 1 having no value may be zero matrices of size (W, W) containing all zero elements. Accordingly, the initial parity check matrix may comprise protograph matrices that are zero matrices and protograph matrices that are nonzero matrices, e.g. cyclically shifted identity matrices.
In Table 1, the first 18 columns may represent a systematic section of the parity check matrix producing systematic (data) bits at the output of the encoder 402, and the last six columns may represent a parity check section of the parity check matrix generating the parity bits 406 from the input data bits 400. It should be appreciated that Table 1 represents only an example of the parity check matrix, and another parity check matrix may be generated by using a different combination of cyclically shifted protograph matrices. Also, the size of the matrix is dependent on the implementation.
After processing the data bits 400 with the initial parity check matrix 404, the LDPC encoder 402 outputs the parity bits 406. The data bits 404 and the parity bits 406 may be transmitted in a message through a radio channel to the receiver. We remind that further transmitter and receiver components are typically provided between the encoder 402 and a decoder 408 to carry out signal processing related to the transmission and reception of radio signals, but these components have been omitted from
In some embodiments, the transmitter may transmit only a subset of parity bits generated by the encoder 402. The operation of the transmitter and the receiver may be aligned such that both devices have the knowledge of which parity bits are transmitted and available to the receiver for the decoding.
In this embodiment, the overlapping matrix 500 may be of the same size as the initial parity check matrix 404. In that case, the overlapping matrix overlaps fully with the initial parity check matrix. In another embodiment, the overlapping matrix 500 may be of different size, e.g. smaller than the initial parity check matrix 404. Accordingly, the overlapping matrix 500 overlaps with the initial parity check matrix only partially. In such a case, the positioning of the overlapping between the two matrices may be selected according to implementation, and only the overlapping elements are combined, e.g. summed together. The values in Table 2 have the same meaning as in Table 1, i.e. cyclic shifts of the identity matrix.
The combining may be considered on different levels of notation in a slightly different manner. For example, when using the protograph notation used in Tables 1 and 2 above where a single box represents a protograph matrix, the combination may be carried out by applying the values of the overlapping matrix of Table 2 to the corresponding locations in the initial parity check of Table 1 such that the original value of the initial parity check matrix is also maintained. For example, a value of the box on the second row, first column of the combined matrix would become (62, 38) where ‘62’ is obtained from the initial parity check matrix and ‘38’ from the overlapping matrix. However, when using a full matrix notation where the protograph matrices are expanded into “real” binary LDPC matrices, the combining may be summation, modulo2 summation, or another combination of binary values of the binary matrices.
The effect of using the overlapping matrix 500 combined with the initial parity check matrix 404 is that some protograph matrices of the new parity check matrix have more than one cyclic nonzero diagonals. Here is one example of such a protograph matrix with W=5:
The new parity check matrix may be computed beforehand and stored in a memory of the transmitter. Now, the transmitter may use the encoder 402 to reencode the data bits 400. Since the parity check matrix is different from the one used in the initial transmission in
Again, the parity bits 502 are corrupted by noise in the channel, and the receiver receives corrupted parity bits 503. The receiver may input the corrupted parity bits to the decoder together with the soft values of the decoded data bits 410 acquired as a result of decoding the received message of the initial transmission. Another input to the decoder 408 may be the new parity check matrix formed in the receiver in the same manner as in the transmitter by combining the initial parity check matrix 404 with the overlapping matrix 500. The receiver may also store the resulting parity check matrix beforehand in order to reduce computation at the time of performing the decoding. As a result of the decoding, the decoder 408 outputs new estimates of the transmitted data bits 504.
Now, the receiver may check the decoded parity bits or run another CRC to verify whether or not the estimated data bits 504 are the transmitted data bits 400. If the result indicates successful decoding, the receiver may send ACK to the transmitter. Otherwise, the decoder still has not successfully decoded the data bits, and the receiver may send NACK to the transmitter or send no ACK.
Referring to
The overlapping matrix 600 generates a final parity check matrix where the protograph matrices having multiple nonzero diagonals are at different locations than in the embodiment of
As in the embodiment of
Again, the parity bits 602 are corrupted by noise in the channel, and the receiver receives corrupted parity bits 603. The receiver may input the corrupted parity bits 603 to the decoder together with the soft values of the decoded data bits 504 acquired as a result of decoding the received message of the initial transmission and the first retransmission. Another input to the decoder 408 may be the new parity check matrix formed in the receiver in the same manner as in the transmitter by combining the initial parity check matrix 404 with the second overlapping matrix 600. The receiver may also store the resulting parity check matrix beforehand in order to reduce computation at the time of performing the decoding. As a result of the decoding, the decoder 408 outputs new estimates of the transmitted data bits 604.
Now, the receiver may run another CRC to verify whether or not the estimated data bits 604 are the transmitted data bits 400. If the result indicates successful decoding, the receiver may send ACK to the transmitter. Otherwise, the decoder still has not successfully decoded the data bits, and the receiver may send NACK to the transmitter or send no ACK.
Let us now consider the embodiment of
The overlapping matrix 700 generates a final parity check matrix having some protograph matrices having two nonzero diagonals (weight two) and even some protograph matrices having three nonzero diagonals (weight three). As already illustrated above below Table 2, the number of nonzero diagonals may be considered in the cyclic manner because the protograph matrices are cyclically shifted identity matrices. Also in this embodiment, the overlapping matrix 700 may be of the same size as the initial parity check matrix 404. In that case, the overlapping matrix overlaps fully with the initial parity check matrix. In another embodiment, the overlapping matrix 700 may be of different size, e.g. smaller than the initial parity check matrix 404. Accordingly, the overlapping matrix 700 overlaps with the initial parity check matrix only partially. In such a case, the positioning of the overlapping between the two matrices may be selected according to implementation, and only the overlapping elements are summed together. The values in Table 4 have the same meaning as in Tables 1 to 3, i.e. cyclic shifts of the identity matrix.
As in the embodiments of
Again, the parity bits 702 are corrupted by noise in the channel, and the receiver receives corrupted parity bits 703. The receiver may input the corrupted parity bits 603 to the decoder together with the soft values of the decoded data bits 504 acquired as a result of decoding the received message of the initial transmission and the first retransmission. Another input to the decoder 408 may be the new parity check matrix formed in the receiver in the same manner as in the transmitter by combining the matrices 701 and 700 by using modulo2 summing. The receiver may also store the resulting parity check matrix beforehand in order to reduce computation at the time of performing the decoding. As a result of the decoding, the decoder 408 outputs new estimates of the transmitted data bits 704.
Now, the receiver may run another CRC or otherwise verify whether or not the estimated data bits 704 are the transmitted data bits 400. If the result indicates successful decoding, the receiver may send ACK to the transmitter. Otherwise, the decoder still has not successfully decoded the data bits, and the receiver may send NACK to the transmitter or send no ACK.
If the second retransmission still results in a failure in the correct decoding of the data bits, the procedure may be continued according to the embodiment of
It should be noted retransmission order listed here as first, second, and so on is simplified from a more general case on Nth, Nth+1 and so on. Nth retransmission may use the parity check matrix mentioned in this document in connection with the first retransmission. Nth+1 retransmission may employ a parity check matrix described in connection with the second retransmission. A retransmission prior to the Nth may retransmission use other retransmission schematics, e.g. a prior art parity check matrix.
Tables 1 to 4 illustrate just examples of the possible constructions of the parity check matrices. There exist numerous other variants of the parity check matrices that may work equally well or even better, and virtually any parity check matrix may be generated according to the principles described above. The principles may include providing the initial parity check matrix with weight 1, indicating that the protograph matrices include zero matrices and matrices having a single cyclic nonzero diagonal. The principles may further include that a modified parity check matrix used in a retransmission may, additionally, include at least one protograph matrix having multiple cyclic nonzero diagonals.
In the embodiments described above, the parity check matrix is modified between the retransmissions, and parity bits of different transmissions are acquired from different parity check matrices. In another embodiment, at least one retransmission comprises parity bits acquired from the same parity check matrix as at least one previous (re)transmission but that the parity bits are different from parity bits transmitted in the at least one previous transmission. For example, the first retransmission may comprise parity bits acquired according to the embodiment of
Referring to
The memory 20 may be implemented using any suitable data storage technology, such as semiconductor based memory devices, flash memory, magnetic memory devices and systems, optical memory devices and systems, fixed memory and removable memory. The memory may comprise a configuration database 24 for storing configuration data for the encoder 402. For example, the configuration database 24 may store the LDPC parity check matrices for encoding the data bits at different stages of the ARQ process, e.g. in the initial transmission, first retransmission, second retransmission, etc.
The apparatus may further comprise a communication interface (TX/RX) 26 comprising hardware and/or software for realizing communication connectivity according to one or more communication protocols. The communication interface 26 may provide the apparatus with communication capabilities to communicate in the cellular communication system and/or in another wireless network. Depending on whether the apparatus is configured to operate as a terminal device, a peer device, or an access node, and depending on a radio access technology, the communication interface may provide different functions. The communication interface 26 may comprise standard wellknown components such as an amplifier, filter, frequencyconverter, (de)modulator, and encoder/decoder circuitries and one or more antennas. The communication interface 26 may comprise radio interface components providing the apparatus with radio communication capability in one or more wireless networks.
Referring to
The communication control circuitry 10 may further comprise an LDPC encoder 18 configured to encode control plane and/or data plane messages before transmission through the communication interface 26. The LDPC encoder 18 may incorporate the encoder 402 described above and, additionally, it may include a parity check matrix generator 14 configured to generate the parity check matrix for the encoder 402 in the abovedescribed manner. The parity check matrix generator 14 may be configured to determine whether a message currently being processed for transmission is an initial transmission of a message, a first retransmission, a second retransmission, etc. and select the appropriate LDPC parity check matrix, as described above in connection with
In an embodiment, the apparatus of
Referring to
The memory 60 may be implemented using any suitable data storage technology, such as semiconductor based memory devices, flash memory, magnetic memory devices and systems, optical memory devices and systems, fixed memory and removable memory. The memory may comprise a configuration database 64 for storing configuration data for the encoder 402. For example, the configuration database 64 may store the LDPC parity check matrices for encoding the data bits at different stages of the ARQ process, e.g. in the initial transmission, first retransmission, second retransmission, etc.
The apparatus may further comprise a communication interface (TX/RX) 66 comprising hardware and/or software for realizing communication connectivity according to one or more communication protocols. The communication interface 66 may provide the apparatus with communication capabilities to communicate in the cellular communication system and/or in another wireless network. Depending on whether the apparatus is configured to operate as a terminal device, a peer device, or an access node, and depending on a radio access technology, the communication interface may provide different functions. The communication interface 66 may comprise standard wellknown components such as an amplifier, filter, frequencyconverter, (de)modulator, and encoder/decoder circuitries and one or more antennas. The communication interface 26 may comprise radio interface components providing the apparatus with radio communication capability in one or more wireless networks.
Referring to
The communication control circuitry 50 may further comprise an LDPC decoder 58 configured to decode control plane and/or data plane messages received through the communication interface 66. The LDPC decoder 58 may incorporate the decoder 408 described above and, additionally, it may include a parity check matrix generator 54 configured to generate the parity check matrix for the decoder 408 in the abovedescribed manner. The parity check matrix generator 54 may be configured to determine whether a message currently being processed is an initial transmission of a message, a first retransmission, a second retransmission, etc. and select the appropriate LDPC parity check matrix, as described above in connection with
In an embodiment, the apparatus of
As used in this application, the term ‘circuitry’ refers to all of the following: (a) hardwareonly circuit implementations, such as implementations in only analog and/or digital circuitry, and (b) combinations of circuits and software (and/or firmware), such as (as applicable): (i) a combination of processor(s) or (ii) portions of processor(s)/software including digital signal processor(s), software, and memory(ies) that work together to cause an apparatus to perform various functions, and (c) circuits, such as a microprocessor(s) or a portion of a microprocessor(s), that require software or firmware for operation, even if the software or firmware is not physically present. This definition of ‘circuitry’ applies to all uses of this term in this application. As a further example, as used in this application, the term ‘circuitry’ would also cover an implementation of merely a processor (or multiple processors) or a portion of a processor and its (or their) accompanying software and/or firmware. The term ‘circuitry’ would also cover, for example and if applicable to the particular element, a baseband integrated circuit or applications processor integrated circuit for a mobile phone or a similar integrated circuit in a server, a cellular network device, or another network device.
The techniques and methods described herein may be implemented by various means. For example, these techniques may be implemented in hardware (one or more devices), firmware (one or more devices), software (one or more modules), or combinations thereof. For a hardware implementation, the apparatus(es) of embodiments may be implemented within one or more applicationspecific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, other electronic units designed to perform the functions described herein, or a combination thereof. For firmware or software, the implementation can be carried out through modules of at least one chipset (e.g. procedures, functions, and so on) that perform the functions described herein. The software codes may be stored in a memory unit and executed by processors. The memory unit may be implemented within the processor or externally to the processor. In the latter case, it can be communicatively coupled to the processor via various means, as is known in the art. Additionally, the components of the systems described herein may be rearranged and/or complemented by additional components in order to facilitate the achievements of the various aspects, etc., described with regard thereto, and they are not limited to the precise configurations set forth in the given figures, as will be appreciated by one skilled in the art.
Embodiments as described may also be carried out in the form of a computer process defined by a computer program or portions thereof. Embodiments of the methods described in connection with
Even though the invention has been described above with reference to an example according to the accompanying drawings, it is clear that the invention is not restricted thereto but can be modified in several ways within the scope of the appended claims. Therefore, all words and expressions should be interpreted broadly and they are intended to illustrate, not to restrict, the embodiment. It will be obvious to a person skilled in the art that, as technology advances, the inventive concept can be implemented in various ways, e.g. applied in connection with other channel codes than the LDPC codes. Further, it is clear to a person skilled in the art that the described embodiments may, but are not required to, be combined with other embodiments in various ways.