CLOCK TRANSMISSION METHOD AND RELATED DEVICE

• US 20190312717A1
• Filed: 06/23/2019
• Published: 10/10/2019
• Est. Priority Date: 12/23/2016
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: WANG, Jinhui, SHI, Xingjian, WU, Feng
• Granted Patent: US 11,177,931 B2
• Time in Patent Office: Days
• CPC Class Codes: H04J 14/08 Time-division multiplex systems
• CPC Class Codes: H04J 2203/0026 Physical details
• CPC Class Codes: H04J 2203/0075 Connection-oriented
• CPC Class Codes: H04J 3/0647 Synchronisation among TDM nodes
• CPC Class Codes: H04J 3/0673 using intermediate nodes, e.g. modification of a received timestamp before further transmission to the next packet node, e.g. including internal delay time or residence time into the packet
• CPC Class Codes: H04J 3/1652 Optical Transport Network [OTN]
• CPC Class Codes: H04L 2212/00 Encapsulation of packets
• CPC Class Codes: H04L 7/0075 with photonic or optical means
• CPC Class Codes: H04Q 11/0066 Provisions for optical burst or packet networks
• CPC Class Codes: H04W 88/085 Access point devices with remote components

Abstract

Embodiments relate to optical transport technologies, and more specifically, to a clock transmission method. Under this method, a first optical data unit (ODU) container can be obtained. Phase discrimination can be performed on an obtained first clock and a first ODU clock of a transmit end, to generate a first PD value. The first

PD value can then be inserted into an overhead of the first ODU container. The first ODU container can be encapsulated into a second ODU container, and the second ODU container can be sent. A rate of the second ODU container is higher than a rate of the first ODU container. The first PD value is transmitted in the first ODU container which is not decapsulated in a subsequent transmission process. Therefore, final recovery of the first clock is not affected, so that a deviation between a finally recovered clock and the first clock is greatly reduced.

Claims

1. A clock transmission method comprising:

obtaining, by a transmit end, a first optical channel data unit (ODU) container;

performing, by the transmit end, phase discrimination (PD) on an obtained first clock and a first ODU clock of the transmit end, to generate a first PD value;

inserting, by the transmit end, the first PD value into an overhead of the first ODU container;

encapsulating, by the transmit end, the first ODU container into a second ODU container, wherein a rate of the second ODU container is higher than a rate of the first ODU container; and

sending the second ODU container.

2. The clock transmission method according to claim 1, wherein the method further comprises:

receiving, by the transmit end, a transmission service; and

obtaining, by a transmit end, the first ODU container comprises;

encapsulating, by the transmit end, the received transmission service into the first ODU container.

3. The clock transmission method according to claim 2, wherein the method further comprises:

recovering, by the transmit end, the first clock from the transmission service.

4. The clock transmission method according to claim 2, wherein the transmission service is a CBR service;

and

encapsulating, by the transmit end, the received transmission service into the first ODU container comprises;

encapsulating, by the transmit end, the received CBR service into the first ODU container through a Bit-synchronous Mapping Procedure (BMP).

5. The clock transmission method according to claim 3, wherein the transmission service is a CBR service;

and

encapsulating, by the transmit end, the received transmission service into the first ODU container comprises;

encapsulating, by the transmit end, the received CBR service into the first ODU container through a Bit-synchronous Mapping Procedure BMP.

6. An OTN device, comprising:

a memory, configured to store computer-executable program code; and

at least one processor, coupled to the memory, wherein

the program code comprises one or more instructions, and when executed by the at least one processor, the one or more instructions cause the at least one processor to perform the following;

obtaining a first ODU container;

performing phase discrimination on an obtained first clock and a first ODU clock of the OTN device, to generate a first PD value;

inserting the first PD value into an overhead of the first ODU container;

encapsulating the first ODU container into a second ODU container, wherein a rate of the second ODU container is higher than a rate of the first ODU container; and

sending the second ODU container.

7. The OTN device according to claim 6, wherein the at least one processor is further caused to perform:

receiving a transmission service; and

encapsulating the received transmission service into the first ODU container.

8. The OTN device according to claim 7, wherein the at least one processor is further caused to perform:

recovering the first clock from the transmission service.

9. The OTN device according to claim 7, wherein the transmission service is a CBR service, and the at least one processor is caused to perform:

encapsulating the received CBR service into the first ODU container through a Bit-synchronous Mapping Procedure (BMP).

10. The OTN device according to claim 8, wherein the transmission service is a CBR service, and the at least one processor is caused to perform:

encapsulating the received CBR service into the first ODU container through a BMP.

11. An OTN device, comprising:

a memory, configured to store computer-executable program code; and

at least one processor, coupled to the memory, wherein

the program code comprises one or more instructions, and when executed by the at least one processor, the one or more instruction cause the at lease one processor to perform the following;

receiving a second ODU container;

obtaining a second ODU clock of the second ODU container;

performing phase discrimination on the second ODU clock and a second clock of the OTN device, to generate a fourth PD value;

performing a difference calculation on the fourth PD value and a third PD value borne in the second ODU container, to obtain a fifth PD value, wherein the third PD value is obtained after a difference calculation is performed on a first PD value and a second PD value, the second PD value is generated after phase discrimination is performed on a first ODU clock and the second ODU clock, the first PD value is obtained after phase discrimination is performed on a first clock and the first ODU clock, the first ODU clock is an ODU clock of a generation end of the first PD value, and the first clock is obtained by the generation end; and

adjusting the second clock as the first clock based on the fifth PD value, and output the first clock.

12. The OTN device according to claim 11, wherein the at least one processor is caused to perform:

de-capsulating the second ODU container to a first ODU container through a GMP; and

performing the difference calculation on the third PD value in the first ODU container and the fourth PD value, to obtain the fifth PD value.

13. The OTN device according to claim 12, wherein the first ODU container further bears a transmission service, and the at least one processor is further caused to perform:

de-capsulating the first ODU container though a BMP, to obtain the transmission service.

14. The OTN device according to claim 13, wherein the transmission service is a CBR service, the first clock is a CBR clock that is recovered by the generation end from the transmission service, and the second clock is a second CBR clock.

15. The OTN device according to claim 11, wherein the at least one processor is further caused to perform:

performing a loop low-pass filter (LPF) calculation based on the fifth PD value, to obtain a frequency control word; and

tuning a local oscillator based on the frequency control word, to output the first clock.

16. The OTN device according to claim 12, wherein the at least one processor is further caused to perform:

performing a loop low-pass filter (LPF) calculation based on the fifth PD value, to obtain a frequency control word; and

tuning a local oscillator based on the frequency control word, to output the first clock.

17. The OTN device according to claim 13, wherein the at least one processor is further caused to perform:

performing a loop low-pass filter (LPF) calculation based on the fifth PD value, to obtain a frequency control word; and

tuning a local oscillator based on the frequency control word, to output the first clock.