DECISION FEEDBACK EQUALIZER AND INTERCONNECT CIRCUIT

• US 20190312757A1
• Filed: 06/25/2019
• Published: 10/10/2019
• Est. Priority Date: 01/31/2017
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Sakai, Yasufumi
• Granted Patent: US 10,728,058 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H03K 5/003 Changing the DC level reinsertion of dc component of a television signal H04N5/16
• CPC Class Codes: H03K 5/24 the characteristic being amplitude
• CPC Class Codes: H03K 5/249 using clock signals
• CPC Class Codes: H04B 3/04 Control of transmission; Equalising
• CPC Class Codes: H04L 25/03 Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence

Abstract

A decision feedback equalizer includes: a comparison circuit; a latch circuit configured to latch a result of comparison by the comparison circuit; a setting circuit configured to set a decision threshold of the comparison circuit in accordance with a control signal; and a switch circuit configured to be controlled to be turned on and off by an output signal from the latch circuit, wherein the setting circuit is configured to be connected in parallel with an input stage of the comparison circuit through the switch circuit and operate in synchronization with a clock signal for driving the comparison circuit.

Claims

1. A decision feedback equalizer comprising:

a comparison circuit;

a latch circuit configured to latch a result of comparison by the comparison circuit;

a setting circuit configured to set a decision threshold of the comparison circuit in accordance with a control signal; and

a switch circuit configured to be controlled to be turned on and off by an output signal from the latch circuit,

wherein the setting circuit is configured to be connected in parallel with an input stage of the comparison circuit through the switch circuit and operate in synchronization with a clock signal for driving the comparison circuit.

2. The decision feedback equalizer according to claim 1, wherein the setting circuit is configured to control a threshold adjustment transistor in accordance with the control signal, the threshold adjustment transistor being coupled to the input stage via the switch circuit in parallel.

3. The decision feedback equalizer according to claim 2, wherein the setting circuit is configured to control the threshold adjustment transistor by using control voltage having a voltage value that linearly changes with the control signal.

4. The decision feedback equalizer according to claim 3, wherein the setting circuit includes a digital-analog converter configured to convert the control signal that is digital into the control voltage that is analog.

5. The decision feedback equalizer according to claim 1,

wherein the comparison circuit includes an offset adjustment circuit connected with the input stage, and

wherein the offset adjustment circuit is configured to adjust an offset of the decision threshold.

6. The decision feedback equalizer according to claim 1, wherein the input stage includes a P-channel differential pair.

7. The decision feedback equalizer according to claim 1, wherein the switch circuit includes a complementary switch, the complementary switch being configured to be controlled to be turned on and off by the output signal from the latch circuit.

8. The decision feedback equalizer according to claim 1, wherein the latch circuit is configured not to be controlled by a clock signal.

9. The decision feedback equalizer according to claim 1, further comprising a time interleaved configuration.

10. The decision feedback equalizer according to claim 1, further comprising a two-parallel or four-parallel time interleaved configuration.

11. The decision feedback equalizer according to claim 1,

wherein the comparison circuit includes (2ⁿ−

1) or 2×

(2ⁿ−

1) comparators, each comparator being configured to compare 2ⁿ-valued (n is a natural number) pulse amplitude modulation signals,

wherein the latch circuit includes (2ⁿ−

1) or 2×

(2ⁿ−

1) latch elements, each latch element being configured to latch a result of comparison by the comparator,

wherein the setting circuit includes (2ⁿ−

1) or 2×

(2ⁿ−

1) threshold setting circuits, each threshold setting circuit being configured to set the decision threshold of the comparator, and

wherein the switch circuit includes (2ⁿ−

1) or 2×

(2ⁿ−

1) switch elements, each switch element being configured to be controlled to be turned on and off by the output signal from the latch element.

12. The decision feedback equalizer according to claim 11, wherein the value n is two.

13. The decision feedback equalizer according to claim 11, wherein the value n is three.

14. An interconnect circuit comprising:

a transmission device; and

a reception device,

wherein the reception device includes a decision feedback equalizer, the decision feedback equalizer being configured to shape a signal transmitted from the transmission device,

wherein the decision feedback equalizer includes

a comparison circuit,

a latch circuit configured to latch a result of comparison by the comparison circuit,

a setting circuit configured to set a decision threshold of the comparison circuit in accordance with a control signal,

a switch circuit configured to be controlled to be turned on and off by an output signal from the latch circuit, and

wherein the setting circuit is configured to be connected in parallel with an input stage of the comparison circuit through the switch circuit and operate in synchronization with a clock signal for driving the comparison circuit.