APPARATUS AND METHODS FOR ENHANCING SIGNALING BANDWIDTH IN AN INTEGRATED CIRCUIT PACKAGE

• US 20190313523A1
• Filed: 10/31/2018
• Published: 10/10/2019
• Est. Priority Date: 04/04/2018
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Ngo, Thomas T., Ding, Xinlei, Wu, Dance, Shih, Chengchih, Li, Zhiqiang
• Granted Patent: US 10,880,991 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2223/6611 Wire connections
• CPC Class Codes: H01L 2223/6638 Differential pair signal lines
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/4823 connecting the wire to a pin of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49173 Radial fan-out arrangements
• CPC Class Codes: H01L 2224/49433 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 23/49 wire-like arrangements or pins or rods using optical fibres H01L23/48; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/46 of a plurality of wire connectors
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0236 Electromagnetic band-gap structures
• CPC Class Codes: H05K 1/0243 Printed circuits associated with mounted high frequency components
• CPC Class Codes: H05K 1/0245 Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
• CPC Class Codes: H05K 2201/10689 Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]

Abstract

Embodiments described herein provide an electronic device having an integrated circuit disposed in a surface mount package. The surface mount integrated circuit package comprises a first pin and a second pin of the integrated circuit configured to couple the integrated circuit to a first terminal and a second terminal disposed on a circuit board. The first pin and second pin define a first connector and a second connector of a differential connector pair in the surface mount integrated circuit package for transferring differential signals from the integrated circuit to the circuit board. The surface mount integrated circuit package comprises an isolation stud disposed between the first pin and the second pin. The isolation stud is disconnected from the integrated circuit and configured to enlarge a gap between the first pin and the second pin relative to respective gaps of other pins coupling the electronic device to the circuit board.

Claims

1. An electronic device having an integrated circuit disposed in a surface mount package, comprising:

a first pin of the integrated circuit configured to couple the integrated circuit to a first terminal disposed on a circuit board, the first pin defining a first connector of a differential connector pair in the surface mount integrated circuit package for transferring differential signals from the integrated circuit to the circuit board;

a second pin of the integrated circuit configured to couple the integrated circuit to a second terminal disposed on the circuit board, the second pin defining a second connector of the differential connector pair in the surface mount integrated circuit package, wherein the second pin is disposed adjacent to the first pin; and

an isolation stud disposed between respective distal ends of the first pin and the second pin, relative to the integrated circuit, the isolation stud being disconnected from the integrated circuit and configured to enlarge a gap between the first pin and the second pin relative to respective gaps of other pins coupling the electronic device to the circuit board.

2. The device of claim 1, wherein the surface mount integrated circuit package is a low profile Quad Flat Package.

3. The device of claim 1, wherein the isolation stud is part of or coupled to a third terminal of the circuit board between the first terminal and the second terminal.

4. The device of claim 1, further comprising:

a first ground pin adjacent to the first pin configured to couple the integrated circuit to a ground terminal disposed on the circuit board, and a second ground pin adjacent to the second pin configured to couple the integrated circuit to the ground terminal disposed on the circuitry board.

5. The device of claim 1, wherein the differential connector pair is configured to transmit a pair of differential signals from the integrated circuit to the circuit board.

6. The device of claim 1, wherein the differential connector pair is configured to transfer a pair of differential signals received at the circuit board to the integrated circuit.

7. The device of claim 1, wherein the isolation stud is disposed between the respective distal ends of the first pin and the second pin to enlarge the gap between the respective distal ends of the first pin and the second pin to reduce a level of interference caused by the first connector on the second connector and to reduce a level of interference caused by the second connector on the first connector.

8. The device of claim 1, wherein the first connector and the second connector that are separated by an isolation stud transfer differential signals at an increased bandwidth relative to pairs of connectors not separated by a corresponding isolation stud.

9. A method for manufacturing an electronic device having an integrated circuit packaged in a surface mount circuit package, the method comprising:

placing a first pin configured to couple the integrated circuit to a first terminal disposed on a circuit board, the first pin defining a first connector of a differential connector pair in the surface mount integrated circuit package for transferring differential signals from the integrated circuit to the circuit board;

placing a second pin coupling the integrated circuit to a second terminal disposed on the circuit board, the second pin defining a second connector of the differential connector pair in the surface mount integrated circuit package, wherein the second pin is disposed adjacent to the first pin; and

placing an isolation stud disposed between respective distal ends of the first pin and the second pin, relative to the integrated circuit, the isolation stud being disconnected from the integrated circuit and configured to enlarge a gap between the first pin and the second pin relative to respective gaps of other pins coupling the electronic device to the circuit board.

10. The method of claim 9, wherein the surface mount integrated circuit package is a low profile quad flat package.

11. The method of claim 9, wherein the isolation stud is part of or coupled to a third terminal of the circuit board between the first terminal and the second terminal.

12. The method of claim 9, further comprising:

placing a first ground pin adjacent to the first pin configured to couple the integrated circuit to a ground terminal disposed on the circuit board and placing a second ground pin adjacent to the second pin configured to couple the integrated circuit to the ground terminal disposed on the circuitry board.

13. The method of claim 9, further comprising:

transmitting, using the differential connector pair, a pair of differential signals from the integrated circuit to the circuit board.

14. The method of claim 9, further comprising:

transferring, using the differential connector pair of differential signals received at the circuit board to the integrated circuit.

15. The method of claim 9, further comprising:

placing the isolation stud between the respective distal ends of the first pin and the second pin to enlarge the gap between the respective distal ends of the first pin and the second pin to reduce a level of interference caused by the first connector on the second connector and to reduce a level of interference caused by the second connector on the first connector.

16. The method of claim 9, further comprising:

transferring, using the first connector and the second connector that are separated by an isolation stud, differential signals at an increased bandwidth relative to pairs of connectors not separated by a corresponding isolation stud.