CORELESS PACKAGE ARCHITECTURE FOR MULTI-CHIP OPTO-ELECTRONICS

• US 20190317285A1
• Filed: 09/12/2017
• Published: 10/17/2019
• Est. Priority Date: 04/28/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: LIFF, Shawna M., BRAUNISCH, Henning, GOSSELIN, Timothy A., RAGHAVAN, Prasanna, DENG, Yikang, QIAN, Zhiguo
• Granted Patent: US 10,845,552 B2
• Time in Patent Office: Days
• CPC Class Codes: G02B 6/0005 the light guides being of the fibre type G02B6/0003 takes precedence
• CPC Class Codes: G02B 6/2938 for multiplexing or demultiplexing, i.e. combining or separating wavelengths, e.g. 1xN, NxM
• CPC Class Codes: G02B 6/4269 with heat sinks or radiation fins
• CPC Class Codes: G02B 6/4274 Electrical aspects G02B6/4263 and G02B6/4265 take precedence

Abstract

An optoelectronic apparatus is presented. In embodiments, the apparatus may include a package including a substrate with a first side and a second side opposite the first side, wherein the first side comprises a ball grid array (BGA) field. The apparatus may further include one or more integrated circuits (ICs) disposed on the first side of the substrate, inside the BGA field, that thermally interface with a printed circuit board (PCB), to which the package is to be coupled, one or more optical ICs coupled to the second side and communicatively coupled with the one or more ICs via interconnects provided in the substrate, wherein at least one of the optical ICs is at least partially covered by an integrated heat spreader (IHS), to provide dissipation of heat produced by the at least one optical IC.

Claims

1-25. -25. (canceled)

26. An optoelectronic apparatus comprising:

a package including a substrate with a first side and a second side opposite the first side, wherein the first side comprises a ball grid array (BGA) field;

one or more integrated circuits (ICs) disposed on the first side of the substrate within the BGA field that thermally interface with a printed circuit board (PCB), to which the package is to be coupled; and

one or more optical ICs coupled to the second side and communicatively coupled with the one or more ICs via interconnects provided in the substrate, wherein at least one of the optical ICs is at least partially covered by an integrated heat spreader (IHS), to provide dissipation of heat produced by the at least one optical IC.

27. The apparatus of claim 26, wherein the ICs include one or more of a transceiver or transmitter driver, a transimpedance amplifier (TIA) or a clock and data recovery (CDR) circuit.

28. The apparatus of claim 26, wherein the one or more optical ICs include an optical transmitter or an optical receiver.

29. The apparatus of claim 28, wherein at least one of the ICs is to communicate at frequencies between 10 and 200 Gigahertz (GHz) through the substrate to an optical transmitter provided on an upper surface of the substrate.

30. The apparatus of claim 28, wherein the IHS partially covers the optical transmitter and is coupled to it via a mechanically compliant thermal interface material.

31. The apparatus of claim 26 wherein the ICs on the first side of the package are to contact a copper plane connected to vias, slugs or coins in the PCB via a thermal interface material (TIM).

32. The apparatus of claim 31, wherein the TIM is at least one of:

high K underfill, electrically conductive adhesive or sinterable solder.

33. The apparatus of claim 31, wherein the ICs on the first side of the package have back-side metallization, and the TIM is solder.

34. The apparatus of claim 26, wherein the substrate is coreless, and comprises a prepreg substrate, and wherein the first side of the substrate is attached to the PCB via a ball grid array, the back side of the IC circuits adhesively coupled and an entire cross-section under-filled.

35. The apparatus of claim 34, wherein the underfill is a high thermal conductivity underfill.

36. The apparatus of claim 26, wherein solder balls of the BGA field are provided in at least one of through-mold interconnects, or plated copper pillars that are exposed and then subsequently attached with solder balls.

37. The apparatus of claim 28, wherein one of the ICs is a TIA, and wherein the TIA is coupled, through the substrate, to a photodetector provided above the TIA on the upper surface of the package.

38. The apparatus of claim 37, wherein an additional one of the ICs is an optical transmitter driver, coupled, through the substrate, to an optical transceiver provided above the TIA on the upper surface of the package.

39. The apparatus of claim 37, wherein an additional one of the ICs is a clock and data recovery circuit (CDR), also coupled, through the substrate, to the optical transceiver provided above the TIA on the upper surface of the package.

40. An interconnect structure for coupling an electrical IC to an optical IC, comprising:

a substrate with a first side and a second side opposite the first side, the substrate comprising;

a vertical interconnect structure, the interconnect structure comprising;

multiple metal layers, each metal layer comprising an anode portion at a center, and an extended cathode portion that surrounds the anode,

wherein between the anode portion and the extended cathode portion at each layer there is a void having a defined thickness; and

a defined number and arrangement of interlayer vias, to fine tune a high-frequency performance of the interconnect structure.

41. The interconnect structure of claim 40, wherein the extended cathode portion includes two or more stitching vias.

42. The interconnect structure claim 41, wherein a greater number of stitching vias is provided in the extended cathode structure to decrease inductance and improve shielding of noise from other structures in the package.

43. The interconnect structure of claim 41, wherein the substrate is coreless, and wherein the interconnect structure is further to shield any photocurrent travelling from a top of the interconnect structure through the substrate to an electrical IC coupled to the second side of the substrate.

44. The interconnect structure of claim 43, further comprising:

a photodetector coupled to the first side of the substrate; and

a TIA coupled to the second side of the substrate,

wherein the TIA is coupled, through the interconnect structure, to the photodetector.

45. A method of manufacturing an integrated circuit (IC) package, comprising:

providing a substrate with a first side and a second side opposite the first side;

providing a ball grid array (BGA) field on the first side of the substrate;

disposing one or more electrical integrated circuits (ICs) on the first side of the substrate inside the BGA field to thermally interface with a printed circuit board (PCB) to which the package is to be coupled; and

disposing one or more optical ICs coupled to the second side of the substrate and communicatively coupled with the one or more electrical ICs disposed on the first side of the substrate via interconnects provided in the substrate.

46. The method of claim 45, wherein the substrate is coreless, and further comprising covering at least one of the one or more optical ICs, at least partially, with an integrated heat spreader (IHS), to provide dissipation of heat produced by the at least one optical IC.

47. The method of claim 46, wherein at least one of the ICs is to communicate at a rate greater than or equal to 56 Gigabytes per second (Gbps) through the substrate to at least one of the optical ICs.

48. The method of claim 46, wherein covering includes partially covering an optical transmitter with the IHS and coupling to it via a mechanically compliant thermal interface material.

49. The method of claim 47, wherein one of the electrical ICs is a TIA, and further comprising coupling the TIA, through the substrate, to a photodetector provided above the TIA on the upper surface of the substrate.

50. The method of claim 49, wherein an additional one of the electrical ICs is an optical transmitter driver, and further comprising coupling it, through the substrate, to an optical transmitter provided above the TIA on the upper surface of the substrate.