LEVEL-BASED DROOP DETECTION

• US 20190317546A1
• Filed: 04/16/2018
• Published: 10/17/2019
• Est. Priority Date: 04/16/2018
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: BORN, Richard Martin, KOSONOCKY, Stephen Victor, RODRIGUEZ, Miguel
• Granted Patent: US 11,573,593 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/305 in the event of power-supply fluctuations
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: H03K 5/00006 Changing the frequency modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A power regulator provides current to a processing unit. A clock distribution network provides a clock signal to the processing unit. A level-based droop detector monitors a voltage of the current provided to the processing unit and provides a droop detection signal to the clock distribution network in response to the voltage falling below a first threshold voltage. The clock distribution network decreases a frequency of a clock signal provided to the processing unit in response to receiving the droop detection signal. The level-based droop detector interrupts the droop detection signal that is provided to the clock distribution network in response to the voltage rising above a second threshold voltage. The clock distribution network increases the frequency of the clock signal provided to the processing unit in response to interruption of the droop detection signal.

Claims

1. A method comprising:

providing a clock signal from a clock distribution network to a processing unit;

monitoring a voltage provided to the processing unit;

providing a droop detection signal to the clock distribution network in response to the voltage falling below a first threshold voltage; and

decreasing a frequency of the clock signal by the clock distribution network in response to receiving the droop detection signal.

2. The method of claim 1, further comprising:

interrupting the droop detection signal provided to the clock distribution network in response to the voltage rising above a second threshold voltage; and

increasing the frequency of the clock signal provided to the processing unit by the clock distribution network in response to interruption of the droop detection signal.

3. The method of claim 2, wherein providing the droop detection signal and interrupting the droop detection signal comprises:

providing and interrupting the droop detection signal a plurality of times in response to a plurality of droops in the voltage that occurred during different time intervals.

4. The method of claim 3, wherein durations of the different time intervals range from nanoseconds to milliseconds.

5. The method of claim 2, further comprising:

providing the clock signal at a first frequency prior to the clock distribution network receiving the droop detection signal; and

providing the clock signal at a second frequency in response to the clock distribution network receiving the droop detection signal, wherein the second frequency is lower than the first frequency.

6. The method of claim 5, further comprising:

providing the clock signal at the first frequency in response to interruption of the droop detection signal.

7. The method of claim 6, wherein:

providing the clock signal at the second frequency comprises increasing a number of oscillations between high and low phases of a phase locked loop that generates the clock signal in response to the clock distribution network receiving the droop detection signal; and

providing the clock signal at the first frequency in response to interruption of the droop detection signal comprises decreasing the number of oscillations between the high and low phases of the phase locked loop in response to interruption of the droop detection signal.

8. An apparatus comprising:

a power regulator configured to provide current to a processing unit;

a clock distribution network configured to provide a clock signal to the processing unit;

a level-based droop detector configured to monitor a voltage of the current provided to the processing unit and provide a droop detection signal to the clock distribution network in response to the voltage falling below a first threshold voltage; and

wherein the clock distribution network is configured to decrease a frequency of a clock signal provided to the processing unit in response to receiving the droop detection signal.

9. The apparatus of claim 8, wherein:

the level-based droop detector is configured to interrupt the droop detection signal that is provided to the clock distribution network in response to the voltage rising above a second threshold voltage; and

the clock distribution network is configured to increase the frequency of the clock signal provided to the processing unit in response to interruption of the droop detection signal.

10. The apparatus of claim 9, wherein the level-based droop detector comprises:

a voltage source configured to generate the threshold voltage; and

a comparator configured to compare the threshold voltage generated by the voltage source to the voltage provided to the processing unit, wherein the comparator is configured to generate the droop detection signal based on the comparison.

11. The apparatus of claim 9, wherein the level-based droop detector is configured to provide an interrupt in the droop detection signal a plurality of times in response to a plurality of droops in the voltage that occurred during different time intervals.

12. The apparatus of claim 11, wherein the durations of the different time intervals range from nanoseconds to milliseconds.

13. The apparatus of claim 9, wherein the clock distribution network is configured to:

provide the clock signal at a first frequency prior to the clock distribution network receiving the droop detection signal; and

provide the clock signal at a second frequency in response to receiving the droop detection signal, wherein the second frequency is lower than the first frequency.

14. The apparatus of claim 13, wherein the clock distribution network is configured to provide the clock signal at the first frequency in response to interruption of the droop detection signal.

15. The apparatus of claim 14, wherein the clock distribution network comprises:

a phase locked loop to provide a fixed rate clock signal; and

a digital frequency synthesizer to provide a variable rate clock signal by modifying the fixed rate clock signal.

16. The apparatus of claim 15, wherein the digital frequency synthesizer is configured to provide the clock signal at the second frequency by increasing a number of oscillations between high and low phases of the phase locked loop in response to the clock distribution network receiving the droop detection signal.

17. The apparatus of claim 16, wherein the digital frequency synthesizer is configured to provide the clock signal at the first frequency in response to interruption of the droop detection signal by decreasing the number of oscillations between the high and low phases of the phase locked loop in response to interruption of the droop detection signal.

18. An apparatus comprising:

a power regulator configured to provide current at a voltage;

at least one clock distribution network configured to provide a first clock signal to a first clock domain and a second clock signal to a second clock domain;

a first level-based droop detector configured to monitor the voltage and provide a first droop detection signal to the clock distribution network in response to the voltage falling below a first threshold voltage;

a second level-based droop detector configured to monitor the voltage and provide a second droop detection signal to the clock distribution network in response to the voltage falling below a second threshold voltage;

wherein the at least one clock distribution network is configured to decrease a first frequency of the first clock signal provided to the first clock domain in response to receiving the first droop detection signal; and

wherein the at least one clock distribution network is configured to decrease a second frequency of the second clock signal provided to the second clock domain in response to receiving the second droop detection signal.

19. The apparatus of claim 18, further comprising:

a synchronization network configured to synchronize the first and second clock signals subject to a constraint.

20. The apparatus of claim 19, wherein the synchronization network is configured to synchronize the first and second clock signal such that the first frequency is less than or equal to the second frequency.