STORAGE SYSTEMS WITH GO TO SLEEP ADAPTION
A non-volatile memory system goes into a low-power standby sleep mode to reduce power consumption if a host command is not received within delay period. The duration of this delay period is adjustable. In one set of embodiments, host commands can specify the delay value, the operation types to which it applies, and whether the value is power the current power session or to be used to reset a default value as well. In other aspects, the parameters related to the delay value are kept in a host resettable parameter file. In other embodiments, the memory system monitors the time between host commands and adjusts this delay automatically.
- 1. -17. (canceled)
- 18. A storage device system, comprising:
a memory device configured to operate in a standard mode or in a standby mode, wherein the memory device is configured to operate on commands in the standard mode, and the standby mode is lower in power than the standard mode; and a controller configured to; when a first command is completed in the standard mode, switch a mode of the memory device from the standard mode to the standby mode after a delay period subsequent to the completion of the first command unless a second command is received prior to an end of the delay period, wherein a duration of the delay period is adjustable; when the second command is received prior to the end of the delay period, decrease the duration of the delay period based on a first value; when the second command is received after the end of the delay period, increase the duration of the delay period based on a second value which is different from the first value; and when a command specifying a new duration is received, reset the duration to the new duration.
- View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27)
- 28. A machine-implemented method, comprising:
operating a memory device in a standard mode or in a standby mode, wherein the standard mode allows the memory device to operate on commands, and the standby mode is lower in power than the standard mode; when a first command is completed in the standard mode, switching a mode of the memory device from the standard mode to the standby mode after a delay period subsequent to the completion of the first command unless a second command is received prior to an end of the delay period, wherein a duration of the delay period is adjustable; when the second command is received prior to the end of the delay period, decreasing the duration of the delay period based on a first value; when the second command is received after the end of the delay period, increasing the duration of the delay period based on a second value which is different from the first value; and when a command specifying a new duration is received, resetting the duration to the new duration.
- View Dependent Claims (29, 30, 31, 32, 33, 34)
- 35. An apparatus, comprising:
means for operating a memory device in a standard mode or in a standby mode, wherein the standard mode allows the memory device to operate on commands, and the standby mode is lower in power than the standard mode; when a first command is completed in the standard mode, means for switching a mode of the memory device from the standard mode to the standby mode after a delay period subsequent to the completion of the first command unless a second command is received prior to an end of the delay period, wherein a duration of the delay period is adjustable; when the second command is received prior to the end of the delay period, means for decreasing the duration of the delay period based on a first value; when the second command is received after the end of the delay period, means for increasing the duration of the delay period based on a second value which is different from the first value; and when a command specifying a new duration is received, means for resetting the duration to the new duration.
- View Dependent Claims (36, 37)
This application is a continuation of U.S. application Ser. No. 13/323,612, filed Dec. 12, 2011, now U.S. Published Application No. 2013/0151755, which application is incorporated herein in its entirety by this reference.
This invention relates, generally, to non-volatile memory devices and, more specifically, to such device which optimize their behaviors based upon host behavior.
Various commercially available non-volatile memory cards that are becoming popular are extremely small and have different mechanical and/or electrical interfaces. Examples include the related MultiMediaCard (“MMC”) and Secure Digital (“SD”) memory cards that are available from SanDisk Corporation of Sunnyvale, Calif., assignee of the present application. There are other cards that conform to standards of the International Organization for Standardization (“ISO”) and the International Electrotechnical Commission (“IEC”), an example that is widely implemented being known as the ISO/IEC 7816 standard.
The physical and electrical specifications for the MMC are given in “The MultiMediaCard System Specification” that is updated and published from time-to-time by the MultiMediaCard Association (“MMCA”) of Cupertino, Calif. Versions 2.11 and 2.2 of that Specification, dated June 1999 and January 2000, respectively, are expressly incorporated herein by this reference. MMC products having varying storage capacity up to 64 megabytes in a single card are currently available from SanDisk Corporation, and capacities of 128 megabytes are expected to be available in the near future. These products are described in a “MultiMediaCard Product Manual,” Revision 2, dated April 2000, published by SanDisk Corporation, which Manual is expressly incorporated herein by this reference. Certain aspects of the electrical operation of the MMC products are also described in co-pending patent applications of Thomas N. Toombs and Micky Holtzman, Ser. Nos. 09/185,649 and 09/186,064, both filed Nov. 4, 1998, and assigned to SanDisk Corporation. The physical card structure and a method of manufacturing it are described in U.S. Pat. No. 6,040,622, assigned to SanDisk Corporation. Both of these applications and patent are also expressly incorporated herein by this reference.
The newer SD Card is similar to the MMC card, having the same size except for an increased thickness that accommodates an additional memory chip. A primary difference between them is that the SD Card includes additional data contacts in order to enable faster data transfer between the card and a host. The other contacts of the SD Card are the same as those of the MMC card in order that sockets designed to accept the SD Card will also accept the MMC card. The electrical interface with the SD card is further made to be, for the most part, backward compatible with the MMC product described in version 2.11 of its specification referenced above, in order that few changes to the operation of the host need be made in order to accommodate both types of card. Certain aspects of the SD card are described in U.S. patent application Ser. No. 09/641,023, filed Aug. 17, 2000, which application is incorporated herein by this reference.
Cards made according to the ISO/IEC 7816 standard are of a different shape, have surface contacts in different positions, and a different electrical interface than the MMC and SD Cards. The ISO/IEC 7816 standard has the general title of “Identification cards-Integrated Circuit(s) Cards with Contacts,” and consists of parts 1-10 that carry individual dates from 1994 through 2000. This standard, copies of which are available from the ISO/IEC in Geneva, Switzerland, is expressly incorporated herein by this reference. ISO/IEC 7816 cards are particularly useful in applications where data must be stored in a secure manner that makes it extremely difficult or impossible for the data to be read in an unauthorized manner. The small ISO/IEC 7816 cards are commonly used in cellular telephones, among other applications.
Current storage systems are designed to work with a number of different applications, such as audio storage, still image storage and video storage, but are generally not optimized for a particular application. The different hosts use memory cards in different applications. These applications have different needs in terms of read and write performance, level of data integrity, and so on. Such systems may operate well in one application, but fail to provide acceptable performance in another application. The differentiation in the applications needs is not taken into account in the card controller.
These removable non-volatile memory cards include a memory array and a controller that performs as the memory control and the host interface function. These removable cards are plugged into different a variety of devices, such as personal data assistants (PDAs), digital camera, cell phone, etc., which access the card in different patterns. This differentiation causes the card to have less than optimal performance and capability to optimize the memory management algorithms according to the host access pattern for the various applications. Although general performance enhancements, such as caching, may help in many applications, there will still be trade offs in a general-purpose card. Alternately, there may be specific optimizations for certain applications, but these need to be engineered into the card ahead of time.
According to a first set of aspects, a method is presented of operating a non-volatile memory system, where the memory system includes a non-volatile memory circuit and a controller circuit for managing data stored in the non-volatile memory circuit and the interactions between the memory system and a host to which the memory system is connected. The method includes, while connected to the host, operating of the memory system by the controller circuit in one of either a standard mode or a low-power standby mode. The memory system operates in the standard mode when executing host commands and, after executing a host command, lapsing from the standard mode into the low-power standby mode after a delay unless receiving a further command from the host prior to lapsing into the standby mode. In response to receiving a host command while in the standby mode, the memory system reverts to the standard mode. The method further includes, while connected to the host, operating the memory system according to a set of host commands, wherein the set of host commands includes one or more commands that specify a value for the delay subsequent to the execution of them.
According to other aspects, a non-volatile memory system comprises a non-volatile memory circuit and a controller circuit connected to non-volatile memory circuit. The controller circuit manages the transfer of data between the memory circuit and a host to which the memory system is connected and the storage of the data on the memory system. The controller circuit includes logic circuitry and a volatile random access memory. In response to the memory system not receiving a host command within in a period of time specified by a delay parameter, the controller places the memory system into a low-power standby mode. The controller maintains a first value for the delay parameter in the non-volatile memory circuit, and the controller resets the value of the delay parameter in response to a command that specifies a value for the delay parameter different than the first value.
Further aspects include a method of operating a non-volatile memory system, the memory system including a non-volatile memory circuit and a controller circuit for managing data stored in the non-volatile memory circuit and the interactions between the memory system and a host to which the memory system is connected. The controller circuit operates the memory system in one of either a standard mode or a low-power standby mode, and the memory system executes commands from the host in the standard mode and lapses from the standard mode into the low-power standby mode after a delay value unless receiving a further command from the host prior to lapsing into the standby mode. The method includes monitoring by the controller of a plurality of commands from the host to the memory system; based on said monitoring, determining the time between the commands; and optimizing by the controller of the delay value based on the time between the commands.
Various aspects, advantages, features and embodiments of the present invention are included in the following description of exemplary examples thereof, which description should be taken in conjunction with the accompanying drawings. All patents, patent applications, articles, other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes. To the extent of any inconsistency or conflict in the definition or use of terms between any of the incorporated publications, documents or things and the present application, those of the present application shall prevail.
With reference to
In most of the examples described herein, the SD card is described but it will be understood that the invention is not limited to implementation with any specific type of removable electronic circuit card. In
The SD card 35 contains nine surface electrical contacts 10-18. Contacts 13, 14 and 16 are connected to power (VSS, VDD and VSS2) when inserted into the host system socket 33. Card contact 15 receives a clock signal (CLK) from the host. Contact 12 receives commands (CMD) from the host and sends responses and status signals back to the host. The remaining contacts 10, 1, 17 and 18 (DAT 2, DAT 3, DAT 0 and DAT 1, respectively) receive data in parallel for storage in its non-volatile memory and send data to the host in parallel from the memory. A fewer number of data contacts are selectable for use, such as a single data contact 17. The maximum rate of data transfer between the host and the card is limited by the number of parallel data paths that are used. The MMC card described in the Background above has a similar contact layout and interface, but omits the data pins 10 and 18 and does not use the contact 11, which is provided as a spare. The MMC card has the same dimensions and operates similarly to the SD card except that the card is only 1.4 millimeters thick and has a single data contact 17. The contacts of the card 35 are connected through respective pins 20-28 of the socket 33 to its host system. Other extensions of memory cards that are compatible with the present invention are described in U.S. patent application Ser. No. 09/924,185 filed Aug. 2, 2001, which is hereby incorporated by reference.
The exemplary embodiment of the present invention is based on removable electronic circuit card, structured such as that shown in
As shown in more detail in
Memory cards are used in a wide variety of applications storing different types of data that have different requirements. These include audio, video, digital camera, data capture, error free applications (e.g., medical data) and so on. Although current storage systems are designed in a general manner to work in a number of different applications, such as audio storage, still image storage and video storage, they may operate well in one application but fail to provide fully acceptable performance in another application.
The present invention provides for a variety of cards that may be optimized for a single application or several different applications. For example, an audio-optimized card would “sense” when it is used in an audio device, such as an MP3 player, and know that it will need to maintain a certain data rate output, but may not be required to write data often. Given such information, the controller of the card can periodically output data, and during the dead times performs housekeeping functions and/or go into low power mode. Similarly, a video-optimized card can be developed that could either “sense” it is being used in a video application or, alternatively, the host can inform the card of the fact. A video-optimized card will take other information passed from the host into account, such as: record data rate(s), play back data rate(s), format, compression, quality criteria, sound criteria and other information related to video-applications. Knowing these factors will allow the card to perform optimally for the video-application.
For example, some applications can tolerate more error than others. Such applications, such as a fax or some video applications where single pixel errors are not that noticeable, would not require completely lossless ECC. The memory device can poll the host system to determine whether such a lossy scheme is acceptable. Another example where the loss of a few bits in a sector is not critical is the playing of a coded voice that is saved on a memory card because the decoding can be compensated by the interpolation that is done on data, with each coder/decoder can define its threshold number. On the other hand, more intensive ECC can be performed in applications where data integrity is essential (e.g. medical applications). In this case, the memory device employs more complicated ECC at the cost of performance. Such variable ECC or quality of service ECC is one example of card adapting to the host. Although this may be determined based upon polling the host, the card may also adapt to the host based on the card profiling the host.
In a host profiling arrangement, the non-volatile memory system profiles the host system with which it is used in order to determine the most efficient method of communicating with the host system. The host system of the non-volatile memory system provides feedback to the card to exchange information about a number of criteria. This information could include the type of drivers installed on the host and statistics related to those types of drivers, such as whether they are for video, audio, still images, and so on. It could also include the maximum and minimum clock rates or information about the buffer in the host device (whether the host wants to use the buffer or not) or the buffer in non-volatile system (whether the host wants to use the buffer on the non-volatile system). Based upon the profile of the host established by the card, the card can optimize itself accordingly.
As an example, consider the case where the card would optimize itself based on the frequency of host reads and writes for a card used in an MP3 player. MP3 players do not write often, but they do read a lot, as opposed to cameras that write often and frequently down load to a PC or PDAs that both read and write frequently. Additionally, MP3 players read fairly regularly and not at great speed. Consequently, there is a lot of non-busy time during reads, as shown in
In any of these host-profiling methods, the card controller will identify the host access profile to optimize its algorithms. In addition to a memory array 111 (
As noted, these cards are designed to be plugged into different devices, such as PDAs, digital cameras, cell phones, and so on, which access the card in different patterns. In the prior art, this differentiation in function causes the card a hit in performance and in the capability to optimize the memory management algorithms according to the host access pattern as the prior art lacks the algorithm optimization aspect of the present invention. The different hosts use different applications with the memory cards. These applications have different needs in terms of read/write performance, level of data integrity, etc. that is not taken into account in the prior art card controllers. The host profiling aspect of the present invention improves upon the prior art by having two modes of operation. In the first of these, the host profiling is by the card controller. The second is based on a quality of service negotiation between the card and the host. These operations will allow the card controller to tune its algorithms according to the data collected on the host. The various embodiments can be implemented in hardware or firmware.
In the mode where the host profiling is performed by the card controller, the card will learn about the host during its transactions and will collect information, such as write/read buffer transfer speed, the idle time between data buffers, block count in read/write, LBA rewrites, file access table (FAT) updates, idle time between sequential commands, and so on. The card will then use this information to optimize the memory control algorithms to the host. For example, on a host that reads slowly, such as an MP3 player, the card can handle correctable ECC errors by having the card controller read ahead enough sectors that will allow a safe correction in the flash memory without a degradation in performance. In another example, if the card recognizes rewrites to the file access table, it can have FAT data caching in the card and update these sectors less frequently.
A first example of host profiling by the card'"'"'s controller is the profiling of the clock rate used on the card'"'"'s system bus, for example the SD or MMC bus as described in the references incorporated above for these cards. In this example, the card'"'"'s hardware can include a counter that will be incremented on every system bus clock. Such a counter 133 is shown in
In a further example, the card can set its system clock (or clocks) to meet the host'"'"'s transfer rate and minimize power consumption. As the higher the clock rate, the greater the power consumption of the card'"'"'s controller, the controller'"'"'s system clock(s) have a major impact over the card'"'"'s power consumption. If the card system maintains a clock rate faster than needed to conform with the host'"'"'s transfer rate, unnecessary power will be consumed, so by setting the system clock settings to meet the host transfer rate, the card optimizes its power consumption while maintaining performance. The card'"'"'s firmware can hold a table to indicate the card'"'"'s data transfer rate for a given clock setting. Once the card'"'"'s profiling has determined the host'"'"'s transfer rate, it can then use the minimum clock rates that allow the card to successfully supply the host'"'"'s data transfer rate. This will allow the card'"'"'s power consumption to be optimized. The firmware can continue to monitor the host'"'"'s data transfer rate and update the controller'"'"'s clock(s) setting(s) accordingly.
In another set of examples, the card can profile a host'"'"'s block count for both read and write. Again referring to the SD and MMC cards as the exemplary embodiment, the write and read commands do not have a defined block count and the termination of an operation is based on a stop transmission command. In a first instance, during a reset process, such as power on, the card'"'"'s firmware can determine whether an access by the host is to the file system area instead of the user data area. At reset, the firmware can read assigned area where the Master Boot Record (MBR) is stored, such as Logical Block Address (LBA) 0. If the master boot record is a file system sector, the firmware can find the LBA range of the file system, such as (MBR+Partition Table+FAT1+FAT2) in the MMC/SD card example, where FAT1 and FAT2 are the two copies of the file access table. Once the LBA range of the file system determined, any access to this address space by the host can be considered as access to file system area and not to user area.
In a second instance, the firmware can find the block count used by the host to write data to the user space during write or read operations and the sequence of starting LBAs. Once the card'"'"'s firmware has determined the block count that the host uses and the sequence of starting LBAs, it can tune its algorithms and hardware to maximize performance and minimize power consumption. Examples of such tuning can include data caching, prioritizing tasks/interrupt service routines/direct memory accesses, determine garbage collection (data relocation) preferences (such as least recently used or most recently used blocks), and so on. In systems having multiple Direct Memory Access (DMA) and Interrupt Service Routine (ISR) operations, the priority order chosen can have a major impact on performance.
In the quality of service mode, the host requests the card report its capabilities and recommendation. The host will report to the card the configuration it prefers to work with and its profile for accessing the card. The card capabilities reported to the host can include: read/write speed, best write block count, best start logical block address (LBA) alignment, ECC capabilities correct/ignore/abort, performance versus current consumption, performance versus data retention, and other operating parameters. There are usually a number of trade offs between these in card design, and this process allows these parameters to be adapted to the particular application. The host profile reported to the card can include: write/read maximum speed; logical address offsets for data types (for example, the offset in number of blocks for user data with a start LBA and block count due to overhead, such as (blocks devoted to list of transactions+start LBA+block count) or (blocks devoted to FAT area−start LBA+block count); the level of data integrity in acceptable in a read (for example, ECC errors can be corrected or can be ignored and the read continued; alternately, a bad block can be set to some pattern or the read can be aborted); and so on. All of the features described above for the host-profiling mode can also be implemented in the quality of service mode and vice versa. Additionally, it should be noted that these two modes are not exclusive of each other and be used in a complimentary manner.
As an example of the quality of service mode, if the card knows the memory area storing FATs, it can use a different algorithm to write to these FAT blocks to minimize garbage collections. In another example, if a host, such as a PC, requires high performance and has a high power supply, the card can choose a high performance/high power consumption mode, such as using multiple plane or multi-chip programming (described in U.S. patent application Ser. No. 10/315,451, filed Dec. 9, 2002, which is hereby incorporated by reference); on the other hand, in a low power host, such as an MP3 player, the card can choose low performance and low power operation.
If the controller has the ability to adjust its own internal clock frequency such as by writing a value to a defined hardware register, the controller performance can be adjusted to meet that required by the application and can even be varied depending on external conditions. For example, in a high performance application, a maximum frequency may be desirable at the expense of increased power consumption, and an intelligent controller can measure suitable external variables such as temperature or power supply voltage and adjust the clock frequency accordingly. It is common to design an internal oscillator to be relatively constant with respect to temperature and voltage. However, CMOS circuits are normally capable of higher speed operation at lower temperatures and at higher voltages. The chip temperature can be measured, such as through the use of a temperature sensitive resistor or p-n junction, and the frequency set accordingly. Similarly the external voltage is easily measured using well know analog to digital converter circuitry and the internal oscillator frequency adjusted in response to this measurement. In this manner the application can override the normally pre-set clock frequency and obtain maximum performance under a variety of application and environmental condition.
After the QOS negotiation between the host and the card, the host can set the card'"'"'s configuration according to the host applications'"'"' needs. For instance, an MP3 application may require only require a low bit rate and low power, while an image-capture application may require the maintaining high bit rate, and so on. For example, to use the card in a first application APP 1 610, the host sets the card'"'"'s QOS 611 optimized for the application: for example, it could be an application were the rate and consistency of data transfer is more important that minor amounts of error. In this case, the use of ECC could be used only in as much as it does not affect the transfer rate. At a subsequent time, the host can use the card in another application APP N 620 and resets the card'"'"'s QOS 621 accordingly: For example, application APP N could require data, such as in medical imaging, to be stored at with highest integrity with speed of far less importance.
All of these embodiments have the card learning host profile in real time and tuning the memory management algorithms according the collected information for achieving the best performance. They also differ from the prior art in that the host and card negotiate over capabilities and the card sets the card operating algorithms according to the best configuration.
A particular implementation of the invention based on dynamic optimization through pattern recognition is described with respect to
The techniques of the embodiment of
When a pattern matches the initial portion of a stored command sequence, the card can pre-execute the command sequence corresponding to pattern, as shown at step 509. The actual action taken may depend upon implementation and may be actions in preparation for the command or the actual execution of the command, such as a read operation to fill a cache or doing a seek to an expected location in the memory, preloading control information or tables, or performing logical to physical address translations. Controller 131 (
If step 515 finds that it is not the end of the list, the flow continues to step 519 for the dynamic updating portion of the process. In step 519, the command is executed and the new sequence is stored in the memory, such as RAM 121 of
For example, consider the case where a non-volatile memory is organized into a series of “zones”, such as is described in U.S. patent application Ser. No. 10/315,451 filed Dec. 9, 2002, which is hereby incorporated by reference. In this arrangement, various data used as part of the boot process, such as the file access table (FAT), is stored in a specific area, which can be taken as part of zone 0. When initially accessing a given zone, there is an initial process of logging in to that zone. For example, there may be initial header data associated with each zone that needs to be read (logical to physical conversions, remapping, etc.) and processed before the actual data content is retrieved. By performing this login ahead of time and pre-fetching any likely data, this time is saved if the sequence is as expected, and nothing is lost if it turns out to be different.
In the bottom row of
For example, consider a boot process, where zone 0 is most likely to be accessed (to retrieve the FAT), followed by, say, zone 5 and then zone 1. Based on the initial portion of the sequence, during the dead time after accessing zone 0, the controller may as well login to zone 5 and be ready. If 451, 453, and 455 respectively correspond to the respective combined access times for zones 0, 5, and 1 in the exemplary process, by moving the login and pre-fetch time (453b in
The dynamic optimization through pattern recognition described with respect to
Although the discussion so far has considered the adaptation of a removable electronic circuit card to host behavior, more generally the controller can adapt to the card to other external conditions. For example, it is known that the performance of flash memories, such as those found in the exemplary embodiments above, degrades when operated at extreme temperatures. Further such examples of conditions external to the memory card that may affect card operation are when the battery is low on host device. As noted above, chip temperature can be measured, such as through the use of a temperature sensitive resistor or p-n junction, and the frequency set accordingly. Similarly the external voltage is easily measured using well know analog to digital converter circuitry and the internal oscillator frequency adjusted in response to this measurement. In this manner the application can override the normally pre-set clock frequency and obtain adjust performance to a variety of external conditions.
When the controller senses any of these additional conditions that may adversely affect performance, the controller could operate the memory in a more reliable manner. This could be done in various ways similar to those already described, such as lowering performance, increased use of ECC or margining, and so on. The sensing of such conditions can be accomplished using reference cells in the memory or other techniques, such as described in U.S. Pat. No. 5,694,356, which is hereby incorporated by reference. The particular conditions to which the controller responds, and how it does so, would correspond to the memory technologies (e.g. thin film, MRAM, FRAM, NMOS, etc.) employed.
The forgoing examples memory systems have been based on flash EEPROM memory cells have been described with respect to the type of cell that utilizes conductive floating gates as charge storage elements. However, the various aspects of the present invention can be used in conjunction with the various alternate non-volatile memory technologies (such as thin film, MRAM, FRAM, NMOS, etc.) described in U.S. patent application Ser. No. 10/841,379 filed May 7, 2004, which is hereby incorporated by reference. For example, the invention may also be implemented in a system that uses a charge trapping dielectric as the storage elements in individual memory cells in place of floating gates. Dielectric storage elements are also discussed further in the U.S. patent application serial number U.S. Ser. No. 10/280,352, filed Oct. 25, 2002, which is hereby incorporated by this reference.
The forgoing material is developed more thoroughly in U.S. Pat. Nos. 7,427,027, 7,926,720, and US patent publication number US-2011-0167186-A1.
This section considers embodiments related to when the non-volatile memory device goes into a low-power standby, or sleep, mode. Between commands, the device controller may go to sleep in order to save standby power consumption. For example, the controller may same power by one or more of turning off a clock or oscillator on the device, turning off power to the memory section, turning off power to one or more areas of the controller (such as RAM blocks), and so on. Although the being in the sleep mode saves power, returning the device to the normal operational mode (“waking the device”) upon receiving a new command is both time and power consuming. Although the specifics depend on the scope of the low-power standby mode, waking the device will negatively affect device performance, especially performance for more random host accesses of the device. Consequently, it would help to optimize performance if go to sleep behavior of the memory device better matched the access behavior the host. This section considers mechanisms that help minimize the occurrences of switching between modes and, consequently, minimize the performance impact and the current consumption by increasing the correlation of these mode changes to the host'"'"'s access timing.
In the typical prior art, if the memory device has a sleep mode, the design would use a fixed time delay (of some number of micro- or milliseconds, for instance) before lapsing into a low power standby mode. This means that there will be no performance impact due to returning to the regular operational mode if the host sends commands more frequently than the device delay. A disadvantage of this arrangement is that it does not cover host command timings (from the previous command termination) that are greater than the device delay, resulting in a too frequent lapsing into sleep mode; and, conversely, when the typical host command timing is less that the device delay, the memory system will tend to wait too long before lapsing into the sleep mode. This situation can be aggravated for the case running different applications that use different command timings.
A first set of embodiments uses a command between the host and the memory device to set the device'"'"'s low-power standby mode switch delay (or go-to-sleep delay, STSD). The setting can be per operation or for any command. For instance, if the host is slower in accessing the device upon a set of write commands compared with a set of read commands, the host can define different values for the sleep delays of writes and reads.
The command format can be:
Set Low_Power_Slandby_Mode_SwitchDelay(Operation Type, Delay Time, Attribute) The Operation Type field specifies the types of commands to which the delay applies, such read, write, erase, boot, and so on. The Delay Time filed specifies the go-to-sleep delay number in, for example, microseconds. An Attribute field can be included to specify that delay is permanent or volatile:
- Attribute—PERMANENT: This setting will be used as default after power cycle
- VOLATILE: This setting is used for the current power session
The controller can keep the delay value or values in its RAM 121 (
FIG. 3) or other volatile register memory. An initial or default delay value (or values for differing operation types) can be kept in non-volatile memory, such as in control data kept in the non-volatile mass storage 111, where the PERMANENT designation would cause the corresponding current default value to be updated. While a VOLATILE designation would update the value in RAM 121 only, the PERMANENT designation would update both the value in RAM and that stored in non-volatile memory.
- VOLATILE: This setting is used for the current power session
- Attribute—PERMANENT: This setting will be used as default after power cycle
According to a second set of aspects, in some embodiments the low power standby mode switch delay (GTSD) is set in the memory system'"'"'s parameter file that holds various operational parameters used by the controller during the operation of the memory system. The values initially in the parameter file 171 (
In a complementary set of embodiments, the device monitors the host delay time automatically, acting as a learning system. Based on this monitoring, the controller can adjust the delay values to optimize the memory systems algorithms for going to sleep with respect to the host'"'"'s behavior. In an exemplary embodiment, the input values are:
Default GTSD value—Initial GTSD value after power up from parameter file or host
- Maximum GTSD value—Maximum GTSD value from parameter file or host
The variables used are:
- Current GTSD (C-GTSD) value
After power up this variable equals the default GTSD value and then the value changes after each command as described below with respect to
- Maximum GTSD value—Maximum GTSD value from parameter file or host
If the next command arrives before the system is switched to low-power standby mode (“YES” path out of 803), the new C-GTSD value is calculated (805) based on this fact. This can be done by an algorithm based on the current C-GTSD value and the amount of time after the preceding command when the next command arrived (TNC). (If this is the first command after initialization, the time since initialization can be used as the TNC value or this step can be skipped for this first command.) For example, one sample algorithm is:
In this example, the average of the two values is used, but more generally other intermediate values can be used, and can be a settable parameter for the system or dynamically determined by the controller. Also, more complicated algorithms may be used that are based more than one TNC value, although this will require more storing more data and more involved computations.
This new value is then saved (807) as the current GTSD value and received command is processed (809). At 807, the current delay (C-GTSD) is stored in RAM and, depending on the embodiment, stored in non-volatile memory as the new default value, much as described above for the host command based embodiment. Although shown as occurring sequentially in the order 805-807-809, the order can be arranged, including having these steps overlap. After processing the command and 809, the memory system then loops back to 803 and waits until the next command comes in.
If the next command arrives when the system is already in low-power standby mode (“NO” path out of 803), the memory system will have switched to the low-power standby mode while waiting for the next command, at which point it will revert to the full power, regular mode (811). The new C-GTSD value can be calculated (813) by an algorithm based on the current C-GTSD and the maximum GTSD (M-GTSD) value, increasing it from the current values part way toward the maximum. One example for an algorithm is:
This adds some to the C_GTSD value, without taking it beyond the maximum. Other shifts besides a tenth could similarly be used, as long as it does not reach the maximum, and this fraction can be a settable parameter for the system or dynamically determined by the controller. As with 805, more complicated algorithms could also be used based more than one inter-command period. The process then proceeds on to 815 and 817, which are much as in 807 and 809 and for which similar comments apply.
The flow of
Returning back to controller determined delay embodiment of
For any of the described embodiments, these have the advantage of providing minimal low-power/regular mode switching overhead to gain maximum input/output operation rate for any host and any host application use case, whereas the previous approaches are based on a static solution to provide a fixed response for all hosts and applications
The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.