METHOD AND APPARATUS FOR ENSURING DATA CONSISTENCY

• US 20190317692A1
• Filed: 06/27/2019
• Published: 10/17/2019
• Est. Priority Date: 12/21/2016
• Status: Active Grant

• Current Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Original Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Inventors: Gong, Shaoqin, Gao, Jian, Han, Geng, Gao, Hongpo, Sun, Ree Lei, Xu, Xinlei
• Granted Patent: US 10,831,402 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1438 Restarting or rejuvenating
• CPC Class Codes: G06F 11/2056 by mirroring
• CPC Class Codes: G06F 11/2064 while ensuring consistency
• CPC Class Codes: G06F 11/2082 Data synchronisation
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD

Abstract

Embodiments of the present disclosure provide methods and apparatuses for ensuring data consistency. In some embodiments, a method comprises writing data into a first temporary buffer in a first processor. The method further comprises, in response to the data being written into the first temporary buffer, sending the data to a second processor to update a copy of the data in the second processor. In addition, the method comprises, in response to receiving an indication that the second processor has received the data, copying the data from the first temporary buffer to a first working buffer in the first processor.

Claims

1. An apparatus for ensuring data consistency, comprising:

a first processing unit (processor);

at least one memory coupled to the first processor and storing instructions for execution by the first processor, the instructions, when executed by the first processor, causing the apparatus to;

in response to receiving, from a second processor, data to be updated, write the data into a temporary buffer in the first processor;

in response to the data being written into the temporary buffer, send, to the second processor, an indication that the first processor has received the data; and

copy the data from the temporary buffer to a working buffer in the first processor.

2. The apparatus of claim 1, wherein the instructions, when executed by the first processor, further cause the apparatus to, in response to the data being copied to the working buffer, release the temporary buffer.

3. The apparatus of claim 1, wherein the instructions, when executed by the first processor, further cause the apparatus to:

in response to receiving from the second processor a message indicating that the data has been updated to a temporary region on a disk shared by the first and second processors, obtain, from the message, a flag indicating that the data in the temporary region is valid; and

send, to the second processor, an acknowledgement that the first processor has received the message.

4. The apparatus of claim 3, wherein the instructions, when executed by the first processor, further cause the apparatus to:

in response to receiving from the second processor another message indicating that the data has been updated to a working region on the disk, obtain, from the other message, the flag indicating that the data in the temporary region is invalid; and

send, to the second processor, another acknowledgement that the first processor has received the other message.

5. The apparatus of claim 3 wherein the data is configuration information for the shared disk, the configuration information including state information and a mapping table.

6. The apparatus of claim 1, wherein the instructions, when executed by the first processor, further cause the apparatus to:

in response to determining that the second processor is unresponsive;

write the data into a temporary region on the disk shared by the first and second processors;

in response to the data being written into the temporary region, set a flag associated with the temporary region to indicate that the data in the temporary region is valid;

write the data into a working region on the disk; and

in response to the data being written into the working region, set the flag to indicate that the data in the temporary region is invalid.

7. A storage system for ensuring data consistency, comprising:

a first processing unit (processor) coupled to memory of the first processor;

a second processor coupled to memory of the second processor; and

persistent data storage shared between the first and second processors;

wherein the first processor is configured to;

write data into a temporary buffer in the memory of the first processor;

in response to the data being written into the temporary buffer, send the data to the second processor to update a copy of the data in the memory of the second processor; and

in response to receiving an indication that the second processor has received the data, copy the data from the temporary buffer to a working buffer in the memory of the first processor.

8. The storage system of claim 7, wherein the first processor is further configured to, in response to the data being copied to the working buffer, release the temporary buffer.

9. The storage system of claim 7, wherein the first processor is further configured to:

in response to determining that the second processor is unresponsive, write the data into a temporary region on the shared persistent data storage;

in response to the data being written into the temporary region, set a flag associated with the temporary region to indicate that the data in the temporary region is valid;

after setting the flag associated with the temporary region to indicate that the data in the temporary region is valid, write the data into a working region on the shared persistent data storage; and

in response to the data being written into the working region, set the flag to indicate that the data in the temporary region is invalid.

10. The storage system of claim 7, wherein the second processor is configured to:

in response to receiving, from the first processor, the data to be updated, write the data into another temporary buffer in the memory of the second processor;

in response to the data being written into the other temporary buffer, send, to the first processor, the indication that the second processor has received the data; and

copy the data from the other temporary buffer to another working buffer in the memory of the second processor.

11. The storage system of claim 10, wherein:

the first processor is further configured to, in response to the data being copied to the working buffer, release the temporary buffer; and

the second processor is further configured to, in response to the data being copied to the other working buffer, release the other temporary buffer.

12. The storage system of claim 10, wherein:

the first processor is further configured to;

in response to the data being copied to the working buffer, write the data into a temporary region on the shared persistent data storage;

in response to the data being written into the temporary region, set a flag associated with the temporary region to indicate that the data in the temporary region is valid; and

in response to setting the flag associated with the temporary region to indicate that the data in the temporary region is valid, sending to the second processor a message indicating that the data has been updated to the temporary region, the message including the flag indicating that the data in the temporary region is valid; and

the second processor is further configured to;

in response to receiving from the first processor the message indicating that the data has been updated to the temporary region, obtain, from the message, the flag indicating that the data in the temporary region is valid; and

send, to the first processor, an acknowledgement that the second processor has received the message.

13. The storage system of claim 12, wherein:

the first processor is further configured to;

in response to receiving the acknowledgement that the second processor has received the message, write the data into a working region on the shared persistent data storage;

in response to the data being written into the working region, set the flag to indicate that the data in the temporary region is invalid; and

in response to setting the flag to indicate that the data in the temporary region is invalid, sending to the second processor another message indicating that the data has been updated to the working region, the other message including the flag indicating that the data in the temporary region is invalid; and

the second processor is further configured to;

in response to receiving from the first processor the other message indicating that the data has been updated to the working region, obtain, from the other message, the flag indicating that the data in the temporary region is invalid; and

send, to the first processor, another acknowledgement that the second processor has received the other message.

14. The storage system of claim 7 wherein the data is configuration information for the shared persistent data storage, the configuration information including state information and a mapping table.

15. A computer program product for ensuring data consistency, comprising a non-transitory computer-readable storage medium storing instructions, which, when executed by a first processing unit (processor) of a storage system, cause the storage system to:

write data into a temporary buffer in memory of the first processor;

in response to the data being written into the temporary buffer, send the data to a second processor of the storage system to update a copy of the data in memory of the second processor; and

in response to receiving an indication that the second processor has received the data, copy the data from the temporary buffer to a working buffer in the memory of the first processor.

16. The computer program product of claim 15, wherein the instructions, when executed by the first processor, further cause the storage system to:

in response to the first processor determining that the second processor is unresponsive, write the data into a temporary region on the shared persistent data storage;

in response to the data being written into the temporary region, set a flag associated with the temporary region to indicate that the data in the temporary region is valid;

after setting the flag associated with the temporary region to indicate that the data in the temporary region is valid, write the data into a working region on the shared persistent data storage; and

in response to the data being written into the working region, set the flag to indicate that the data in the temporary region is invalid.

17. The computer program product of claim 15, wherein the instructions, when executed by the second processor, further cause the storage system to:

in response to the second processor receiving, from the first processor, the data to be updated, write the data into another temporary buffer in the memory of the second processor;

in response to the data being written into the other temporary buffer, send, from the second processor to the first processor, the indication that the second processor has received the data; and

copy the data from the other temporary buffer to another working buffer in the memory of the second processor.

18. The computer program product of claim 17, wherein:

the instructions, when executed by the first processor, further cause the storage system to;

in response to the data being copied to the working buffer, write the data into a temporary region on the shared persistent data storage;

in response to the data being written into the temporary region, set a flag associated with the temporary region to indicate that the data in the temporary region is valid; and

in response to setting the flag associated with the temporary region to indicate that the data in the temporary region is valid, sending from the first processor to the second processor a message indicating that the data has been updated to the temporary region, the message including the flag indicating that the data in the temporary region is valid; and

the instructions, when executed by the second processor, further cause the storage system to;

in response to the second processor receiving from the first processor the message indicating that the data has been updated to the temporary region, obtain, from the message, the flag indicating that the data in the temporary region is valid; and

send, from the first processor to the first processor, an acknowledgement that the second processor has received the message.

19. The computer program product of claim 18, wherein:

the instructions, when executed by the first processor, further cause the storage system to;

in response to the first processor receiving the acknowledgement that the second processor has received the message, write the data into a working region on the shared persistent data storage;

in response to the data being written into the working region, set the flag to indicate that the data in the temporary region is invalid; and

in response to setting the flag to indicate that the data in the temporary region is invalid, sending from the first processor to the second processor another message indicating that the data has been updated to the working region, the other message including the flag indicating that the data in the temporary region is invalid; and

the instructions, when executed by the second processor, further cause the storage system to;

in response to the second processor receiving from the first processor the other message indicating that the data has been updated to the working region, obtain, from the other message, the flag indicating that the data in the temporary region is invalid; and

send, from the second processor to the first processor, another acknowledgement that the second processor has received the other message.

20. The computer program product of claim 15 wherein the data is configuration information for the shared persistent data storage, the configuration information including state information and a mapping table.