COMMAND SELECTION POLICY WITH READ PRIORITY

• US 20190317693A1
• Filed: 04/12/2018
• Published: 10/17/2019
• Est. Priority Date: 04/12/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: La Fratta, Patrick A., Walker, Robert M.
• Granted Patent: US 10,725,696 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.

Claims

1. A method for command selection, comprising:

receiving a read command to a memory controller, wherein the read command comprises an address for a bank and a channel of a memory device;

inserting the read command into a queue of the memory controller;

blocking a first number of write commands to the bank;

issuing, to the memory device, an activation command associated with the read command;

blocking a second number of write commands to the channel; and

issuing the read command to the memory device.

2. The method of claim 1, further comprising blocking the second number of write commands after a predetermined duration of time.

3. The method of claim 2, wherein the predetermined duration of time comprises a difference between a row-to-column delay and a write-to-read delay.

4. The method of claim 2, wherein the predetermined duration of time is selected based on a read-after-write dependence associated with the read command.

5. The method of claim 4, further comprising selecting the predetermined duration of time to include a difference between a row-to-column delay and a column-to-column delay based on a determination that the read-after-write dependence is associated with the read command.

6. The method of claim 1, further comprising issuing a row pre-charge command responsive to blocking the first number of write commands to the bank.

7. The method of claim 6, further comprising responsive to determining that a prior write command to a row does not block the read command, issuing the row pre-charge command.

8. The method of claim 6, wherein issuing the activation command further comprises issuing the activation command after issuing the row pre-charge command.

9. The method of claim 8, wherein the activation command is a row activation command.

10. A controller, comprising:

a queue; and

logic configured to;

insert a read command, for a bank and a channel of a memory device, into the queue;

block a first number of write commands to the bank;

issue an activation command associated with the read command;

block a second number of write commands to the channel; and

select the read command for issuance based on a first-ready, first-come, first-served (FRFCFS) policy in which the read command is prioritized over the first number of write commands and the second number of write commands.

11. The controller of claim 10, wherein the logic is further configured to select a write command for issuance to the memory device only if the write command is associated with the read command having a read-after-write dependence.

12. The controller of claim 10, wherein the logic is further configured to select commands from the first number of write commands and the second number of write commands for issuance before the first number of write commands are blocked.

13. The controller of claim 10, wherein the logic is further configured to select commands from the second number of write commands for issuance before the second number of write commands are blocked.

14. The controller of claim 10, wherein the logic is further configured to select commands from a third number of write commands until the read command is selected for issuance.

15. The controller of claim 14, wherein the third number of write commands have a read-after write dependence to the read command and wherein the third number of write commands includes the write command.

16. The controller of claim 15, wherein the third number of write commands are assigned the read-after-write dependent to the read commands responsive to the third number of write commands accessing a same row as the read command.

17. The controller of claim 15, wherein the third number of write commands are assigned an elevated priority over the first number of write commands and the second number of write commands based on the read-after write dependence.

18. A method for command selection, comprising:

receiving, at a memory controller, a read command for a bank and a channel of a memory device;

generating metadata associated with the read command;

determining whether there is a write command with a read-after-write dependence to the read command based on the metadata;

inserting the read command into a prioritized queue;

blocking a first number of write commands to the bank;

issuing an activation command associated with the read command;

blocking a second number of write commands to the channel; and

selecting the write command and the read command for issuance based on a first-ready, first-come, first-served (FRFCFS) policy in response to determining that the write command has the read-after-write dependence to the read command.

19. The method of claim 18, further comprising responsive to determining that the read command does not have the read-after-write dependence, select the read command, from the prioritized queue, for issuance based on the FRFCFS policy.

20. The method of claim 18, wherein processing the read command further comprises determining whether the bank is one of a set of banks with outstanding read commands or elevated write commands.

21. The method of claim 20, further comprising:

inserting a bank identifier (ID) to the set of banks responsive to determining that the bank is not a bank of the set of banks;

marking the write command as having the read-after-write dependence responsive to determining that the write command and the read command access a same row; and

wherein the metadata includes the set of banks and the same row.

22. An apparatus, comprising:

a memory device; and

a memory controller coupled to the memory device and configured to;

iterate through a plurality of commands in a queue and at each iteration;

responsive to determining that a command from the plurality of commands is not a read command, not an elevated write command, and that a first bank identifier (ID) associated with the command is in a list of banks with outstanding reads, execute a bank block and mark the command as not issuable;

responsive to determining that the command is the read command and that the command has a read-after-write dependence, execute the bank block and mark the command as not issuable;

responsive to determining that the command is the read command and that the command does not have the read-after-write dependence, execute a channel block and mark the plurality of commands, excepting the command, as not issuable; and

responsive to determining that the command is an elevated write command, execute the channel block and mark the plurality of commands, excepting the command, as not issuable.

23. The apparatus of claim 22, wherein the memory controller is configured to iterate through the plurality of commands repeatedly over a predetermined interval of time.

24. The apparatus of claim 22, wherein the memory controller is further configured to, at each iteration:

responsive to determining that the command is the read command, that the command does not have the read-after-write dependence, and that there exists a different read command with a different read-after-write dependence through a bank and to an open row, execute a pre-charge block of the bank, execute a bank block, and mark the command as not issuable; and

responsive to determining that the command is the read command, that the command does not have the different read-after-write dependence, and that the different read command with the read-after-write dependence through the bank and to the open row does not exist, execute the channel block and mark the plurality of commands, excepting the command, as not issuable responsive to determining that a predetermined duration of time has expired since the row was activated.

25. The apparatus of claim 22, wherein the memory controller is further configured to, at each iteration:

responsive to determining that the command is an elevated write command and that a predetermined duration of time has expired since the row was activated, execute the channel block and mark the plurality of commands, excepting the command, as not issuable.

26. The apparatus of claim 22, wherein the memory controller is further configured to select a highest priority command with a highest priority, from the queue, using a first-ready, first-come, first-served (FRFCFS) priority.

27. The apparatus of claim 26, wherein the memory controller is further configured to:

insert a current time into a list of activation bank of times responsive to determining that the highest priority command has been activated;

remove a bank activation time from the list of activation bank times responsive to determining that a bank associated with the highest priority command has been pre-charged; and

remove a second bank ID from the list of banks, responsive to determining that the highest priority command is an elevated write command.

29. The method of claim 27, further comprising deprioritizing non-elevated write commands to the partition responsive to deprioritizing the second number of write commands to the channel.

28. A method for command selection, comprising:

receiving a read command to a memory controller, wherein the read command comprises an address of a partition and a channel of a memory device;

inserting the read command into a queue of the memory controller;

deprioritizing a first number of write commands to the partition;

deprioritizing a second number of write commands to the channel; and

selecting the read command to the memory device for issuance from the queue.

30. The method of claim 28, wherein the queue comprises a plurality of registers of the memory controller.