Address Map Caching for a Memory System

• US 20190317894A1
• Filed: 04/12/2018
• Published: 10/17/2019
• Est. Priority Date: 04/12/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Frolikov, Alex
• Granted Patent: US 11,966,329 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/311 In host system
• CPC Class Codes: G06F 2212/313 In storage device
• CPC Class Codes: G06F 2212/466 Metadata, control data
• CPC Class Codes: G06F 2212/656 Address space sharing
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages

Abstract

A memory system having non-volatile media, a volatile memory, and a controller configured to process requests from a host system to store data in the non-volatile media or retrieve data from the non-volatile media. The non-volatile media has a quantity of memory units and stores an address map that defines logical addresses used in the requests in terms of physical addresses of the memory units in the non-volatile media. The host system has a memory connected to the memory system via a communication channel. The memory system has a cache manager that stores a first portion of the address map in the volatile memory of the memory system and a second portion of the address map in the memory of the host system. In response to an operation that uses a logical address defined in the second portion, the cache manager retrieves the second portion of the address map from the memory of the host system through the communication channel to the volatile memory of the memory system.

Claims

1. A memory system, comprising:

non-volatile media having a quantity of memory units;

a volatile memory that stores a first portion of an address map, the address map defining logical addresses in terms of physical addresses of the memory units in the non-volatile media; and

a controller configured to process requests from a host system to store data in the non-volatile media or retrieve data from the non-volatile media, the host system having a memory connected to the memory system via a communication channel;

wherein a cache manager stores a second portion of the address map in the memory of the host system and in response to an operation that uses a logical address defined in the second portion, retrieves the second portion of the address map from the memory of the host system through the communication channel to the volatile memory of the memory system.

2. The memory system of claim 1, wherein the non-volatile media includes a flash memory.

3. The memory system of claim 2, wherein the memory system is a solid-state drive.

4. The memory system of claim 3, wherein in response to the operation that uses a logical address defined in the second portion, the cache manager stores the first portion of the address map from the volatile memory of the memory system through the communication channel into the memory of the host system.

5. The memory system of claim 3, wherein in response to a request to shut down the memory system, the cache manager stores in the non-volatile media portions of the address map in the memory of the host system and in the volatile memory of the memory system.

6. The memory system of claim 5, wherein the first portion of the address map is updated during at least write operations made using logical addresses defined in the first portion of the address map. The memory system of claim 5, wherein during powering up the memory system, the cache manager copies the first portion of the address map from the non-volatile media to the volatile memory and the second portion of the address map from the non-volatile media to the memory of the host system.

10. The memory system of claim 6, wherein the host system and the memory system communicate over the communication channel in accordance with a communication protocol for peripheral component interconnect express bus.

11. The memory system of claim 6, wherein the memory of the host system is accessible to the controller at a speed greater than accessing the non-volatile media.

8. The memory system of claim 7, wherein the memory of the host system is identified to the memory system during the powering up via a base address register.

9. The memory system of claim 8, wherein the memory of the host system includes message queues for communications between the host system and the memory system.

12. A method, comprising:

storing, in non-volatile media of a memory system having a quantity of memory units. an address map, the address map defining logical addresses in terms of physical addresses of the memory units in the non-volatile media;

loading, by a cache manager of the memory system, a first portion of the address map in a volatile memory of the memory system;

processing, by a controller of the memory system, requests from a host system to store data in the non-volatile media or retrieve data from the non-volatile media, the host system having a memory connected to the memory system via a communication channel;

loading, by the cache manager, a second portion of the address map in the memory of the host system; and

in response to an operation that uses a logical address defined in the second portion, retrieving the second portion of the address map from the memory of the host system through the communication channel to the volatile memory of the memory system.

13. The method of claim 12, wherein the non-volatile media includes a flash memory;

the memory system is a solid-state drive;

the host system and the memory system communicate over the communication channel in accordance with a communication protocol for peripheral component interconnect express bus; and

the memory of the host system is accessible to the controller at a speed greater than accessing the non-volatile media.

14. The method of claim 13, further comprising:

in response to the operation that uses a logical address defined in the second portion, storing, by the cache manager, the first portion of the address map from the volatile memory of the memory system through the communication channel into the memory of the host system.

15. The method of claim 13, further comprising:

in response to a request to shutdown the memory system, committing by the cache manager in the non-volatile media portions of the address map cached in the memory of the host system and in the volatile memory of the memory system;

wherein the portions of the address map cached in the memory of the host system and in the volatile memory of the memory system are updated during operations involving logical addresses defined in the portions of the address map.

16. The method of claim 15, further comprising:

during powering up the memory system, copying by he cache manager the first portion of the address map from the non-volatile media to the volatile memory and the second portion of the address map from the non-volatile media to the memory of the host system.

17. The method of claim 16, further comprising:

identifying, during the powering up, the memory of the host system via a base address register.

18. The method of claim 17, further comprising:

receiving, from message queues formed on the memory of the host system, the requests from the host system to store data in the non-volatile media or retrieve data from the non-volatile media, wherein the requests identify memory locations using the logical addresses defined using the address map in terms of the physical addresses of the memory units in the non-volatile media.

19. A non-transitory computer storage medium storing instructions which, when executed by a memory system having non-volatile media, a volatile memory, and a controller, cause the memory system to perform a method, the method comprising:

storing, in the non-volatile media having a quantity of memory units. an address map, the address map defining logical addresses in terms of physical addresses of the memory units in the non-volatile media;

loading a first portion of the address map in a volatile memory of the memory system;

loading a second portion of the address map in the memory of the host system;

processing requests from a host system to store data in the non-volatile media or retrieve data from the non-volatile media, the host system having a memory connected to the memory system via a communication channel; and

in response to an operation that uses a logical address defined in the second portion, swapping through the communication channel the first portion of the address map and the second portion of the address map between the memory of the host system and the volatile memory of the memory system.

20. The non-transitory computer storage medium of claim 19, wherein the method further comprises:

identifying, during powering up of the memory system, the memory of the host system via a base address register; and

receiving, from message queues formed on the memory of the host system, the requests from the host system to store data in the non-volatile media or retrieve data from the non-volatile media, wherein the requests identify memory locations using the logical addresses defined using the address map in terms of the physical addresses of the memory units in the non-volatile media.