Circuit and Method For Managing Access to Memory

• US 20190317902A1
• Filed: 06/27/2019
• Published: 10/17/2019
• Est. Priority Date: 03/29/2017
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Disegni, Fabio Enrico Carlo, Goller, Federico, Febbrarino, Michele
• Granted Patent: US 10,901,919 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1425 the protection being physical, e.g. cell, word, block
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 2212/7207 management of metadata or control data

Abstract

A circuit, for managing operations for accessing a flash memory on the basis of requests received from a main CPU and from an auxiliary CPU, may be configured to: associate with the main CPU, a higher access priority to the flash memory than the access priority of the auxiliary CPU; command, in the absence of further requests for accessing the flash memory, the access to the flash memory for the main or auxiliary CPU which has initiated a first access request; verify, following a receipt of a second access request, the access priority associated with this second access request; suspend one of the first or the second access request having lower priority; and authorize the other of the first or the second access request having higher priority.

Claims

1. An interface circuit for managing access to a memory shared between a first processor and a second processor, the interface circuit comprising:

a timer circuit configured to limit a time interval for access to the memory by the first processor and the second processor, the timer circuit comprising a countdown time interval; and

a conflict manager circuit configured to;

determine that a first request to access the memory is originating from the first processor;

initialize the interface circuit to allow the first processor to access the memory and to prevent the second processor from accessing the memory;

receive a second request to access the memory by the second processor during an execution of a programming and erase subroutine by the first processor;

initiate a countdown time interval using the timer circuit during which the second processor is notified that the second request is accepted and the second request is placed in a state of suspension until an end of the countdown time interval; and

initialize the interface circuit to allow the second processor to access the memory based on determining the end of the countdown time interval and a successful suspension of the execution of the programming and erase subroutine by the first processor.

2. The interface circuit of claim 1, further comprising:

a first register block configured to store requests for accessing the memory from the first processor; and

a second register block configured to store requests for accessing the memory from the second processor.

3. The interface circuit of claim 2, wherein the conflict manager circuit receives the first request from the first register block and the second request from the second register block.

4. The interface circuit of claim 1, further comprising a programming/erase controller (PEC) configured to execute programming and erase subroutines used to program and erase blocks of the memory shared between the first processor and the second processor.

5. The interface circuit of claim 4, further comprising a support memory configured to store programming and erase subroutines used to respectively program and erase blocks of the memory shared between the first processor and the second processor.

6. The interface circuit of claim 5, further comprising a pointer memory configured to:

store a physical address of the support memory; and

provide the programming and erase subroutines stored in the support memory to the PEC.

7. The interface circuit of claim 1, wherein the first processor is a main processing unit and the second processor is an auxiliary processing unit, the main processing unit having an access priority to the memory greater than an access priority of the auxiliary processing unit, the timer circuit further configured to associate a countdown time interval of an operation of the main processing unit to be greater than a countdown time interval of an operation of the auxiliary processing unit.

8. The interface circuit of claim 1, wherein the countdown time interval is a programmable value.

9. A method for managing access to a memory shared between a first processor and a second processor using an interface circuit, the method comprising:

determining that a first request to access the memory is originating from the first processor;

initializing the interface circuit to allow the first processor to access the memory and to prevent the second processor from accessing the memory;

receiving a second request from the second processor to access the memory during an execution of a programming and erase subroutine by the first processor;

initiating a countdown time interval during which the second processor is notified that the second request is accepted and the second request is placed in a state of suspension until an end of the countdown time interval; and

initializing the interface circuit to allow the second processor to access the memory based on determining the end of the countdown time interval and a successful suspension of the execution of the programming and erase subroutine by the first processor.

10. The method of claim 9, wherein the countdown time interval is a first countdown time interval, the method further comprising:

initiating a second countdown time interval at the end of the first countdown time interval, the second processor executing a second programming and erase subroutine until the end of the second countdown time interval; and

initializing the interface circuit to allow the first processor to resume access to the memory to resume execution of the suspended programming and erase subroutine by the first processor based on determining the end of the second countdown time interval.

11. The method of claim 10, further comprising programming the first countdown time interval and the second countdown time interval based on a level of access priority associated with the first request and the second request.

12. The method of claim 10, wherein the first processor is a main processing unit and the second processor is an auxiliary processing unit, the method further comprising programming the first countdown time interval to be greater than the second countdown time interval.

13. The method of claim 9, further comprising storing an address of the memory relating to the suspended programming and erase subroutine by the first processor in a pointer memory.

14. The method of claim 9, further comprising storing, in a support memory of the interface circuit, a binary state condition of the memory indicating whether the memory is being accessed by the first processor or the second processor.

15. A method for managing access to a memory shared between a first processor and a second processor, the method comprising:

allowing the first processor to access the memory and preventing the second processor from accessing the memory;

receiving a request from the second processor to access the memory;

initiating a first countdown time interval in response to the request, an access to the memory by the second processor is suspended during the first countdown time interval; and

initiating a second countdown time interval at an end of the first countdown time interval, the second processor allowed to access the memory and the first processor is prevented from accessing the memory during the second countdown time interval; and

resuming access to the memory by the first processor at the end of the second countdown time interval, the second processor prevented from accessing the memory at the end of the second countdown time interval.

16. The method of claim 15, further comprising storing information associated with an execution by the first processor and the second processor of a corresponding programming and erase subroutine in a support memory during a corresponding suspension of access to the memory.

17. The method of claim 15, wherein the first countdown time interval and the second countdown time interval are programmable countdown time intervals, the method further comprising programming the first countdown time interval and the second countdown time interval in accordance with an access priority level of the first processor and the second processor.

18. The method of claim 15, wherein the first processor is a main processing unit and the second processor is an auxiliary processing unit, the method further comprising programming the first countdown time interval to be greater than the second countdown time interval.

19. The method of claim 15, wherein the first countdown time interval and the second countdown time interval are programmable countdown time intervals, the method further comprising programming the first countdown time interval and the second countdown time interval in accordance with a type of operation to be executed by the first processor and the second processor.

20. The method of claim 15, wherein the first countdown time interval and the second countdown time interval are programmable countdown time intervals, the method further comprising programming the first countdown time interval and the second countdown time interval in accordance with a priority level of programming and erase subroutines to be executed by each of the first processor and the second processor.