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Circuit and Method For Managing Access to Memory

  • US 20190317902A1
  • Filed: 06/27/2019
  • Published: 10/17/2019
  • Est. Priority Date: 03/29/2017
  • Status: Active Grant
First Claim
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1. An interface circuit for managing access to a memory shared between a first processor and a second processor, the interface circuit comprising:

  • a timer circuit configured to limit a time interval for access to the memory by the first processor and the second processor, the timer circuit comprising a countdown time interval; and

    a conflict manager circuit configured to;

    determine that a first request to access the memory is originating from the first processor;

    initialize the interface circuit to allow the first processor to access the memory and to prevent the second processor from accessing the memory;

    receive a second request to access the memory by the second processor during an execution of a programming and erase subroutine by the first processor;

    initiate a countdown time interval using the timer circuit during which the second processor is notified that the second request is accepted and the second request is placed in a state of suspension until an end of the countdown time interval; and

    initialize the interface circuit to allow the second processor to access the memory based on determining the end of the countdown time interval and a successful suspension of the execution of the programming and erase subroutine by the first processor.

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