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METHOD FOR TRIGGERING AND DETECTING A MALICIOUS CIRCUIT IN AN INTEGRATED CIRCUIT DEVICE

  • US 20190318135A1
  • Filed: 04/11/2018
  • Published: 10/17/2019
  • Est. Priority Date: 04/11/2018
  • Status: Active Grant
First Claim
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1. A method for triggering and detecting a malicious circuit on an integrated circuit device, the method comprising:

  • providing a first run of test patterns to logic circuits on the integrated circuit device, the first run of test patterns comprising a plurality of test patterns, each test pattern of the first run of test patterns comprising a plurality of bits, a first portion of the plurality of bits being bits that do not influence a value of a resulting first test output vector, and a second portion of the plurality of bits being bits that will influence the value of the first test output vector;

    outputting the first test output vector from the first run of test patterns;

    comparing the value of the first test output vector to first expected values;

    changing bit values of the first portion of the plurality of bits for each test pattern of the first run of test patterns to generate a second run of test patterns;

    providing the second run of test patterns to the logic circuits on the integrated circuit device;

    outputting a second test output vector resulting from the second run of test patterns; and

    comparing a value of the second run of test patterns to second expected values.

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