METHOD FOR TRIGGERING AND DETECTING A MALICIOUS CIRCUIT IN AN INTEGRATED CIRCUIT DEVICE

• US 20190318135A1
• Filed: 04/11/2018
• Published: 10/17/2019
• Est. Priority Date: 04/11/2018
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: SCHAT, JAN-PETER
• Granted Patent: US 11,023,623 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 11/26 Functional testing
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
• CPC Class Codes: G06F 21/566 Dynamic detection, i.e. detection performed at run-time, e.g. emulation, suspicious activities
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices
• CPC Class Codes: G06F 2221/034 Test or assess a computer or a system

Abstract

A method for triggering and detecting a malicious circuit on an integrated circuit device is provided. A first run of test patterns is provided to logic circuits on the integrated circuit device. Each test pattern of the first run of test patterns includes a plurality of bits, a first portion of the plurality of bits being bits that do not influence a value of a resulting first test output vector, and a second portion of the plurality of bits being bits that will influence the value of the first test output vector. The value of the first test output vector is compared to first expected values. Bit values of the first portion of the plurality of bits for each test pattern of the first run of test patterns are changed to generate a second run of test patterns. The second run of test patterns is provided to the logic circuits on the integrated circuit device. A value of the second run of test patterns is compared to second expected values.

Claims

1. A method for triggering and detecting a malicious circuit on an integrated circuit device, the method comprising:

providing a first run of test patterns to logic circuits on the integrated circuit device, the first run of test patterns comprising a plurality of test patterns, each test pattern of the first run of test patterns comprising a plurality of bits, a first portion of the plurality of bits being bits that do not influence a value of a resulting first test output vector, and a second portion of the plurality of bits being bits that will influence the value of the first test output vector;

outputting the first test output vector from the first run of test patterns;

comparing the value of the first test output vector to first expected values;

changing bit values of the first portion of the plurality of bits for each test pattern of the first run of test patterns to generate a second run of test patterns;

providing the second run of test patterns to the logic circuits on the integrated circuit device;

outputting a second test output vector resulting from the second run of test patterns; and

comparing a value of the second run of test patterns to second expected values.

2. The method of claim 1, wherein the plurality of test patterns are generated by a self-testing circuit on the integrated circuit device.

3. The method of claim 2, wherein the self-testing circuit is characterized as being a logic built-in self-test (LBIST) circuit.

4. The method of claim 1, wherein the first portion of the plurality of bits are characterized as being don'"'"'t care bits, and the second portion of the plurality of bits are characterized as being care bits.

5. The method of claim 1, wherein changing bit values further comprises using a pseudo random number generator to change the bit values.

6. The method of claim 1, wherein the method is for triggering a malicious hardware circuit undetected by production testing.

7. The method of claim 1, wherein the first and second runs of test patterns are generated externally to the integrated circuit device using an automatic test pattern generator (ATPG).

8. The method of claim 1, wherein the logic circuits being tested are realized in a register-transfer level (RTL) design and implemented as registers and combinational logic on the integrated circuit device.

9. A method for triggering and detecting a malicious circuit on an integrated circuit device, the method comprising:

scanning in a first run of test patterns to logic circuits on the integrated circuit device using logic built-in self-test (LBIST), the first run of test patterns comprising a plurality of test patterns, each test pattern of the first run of test patterns comprising a plurality of bits, a first portion of the plurality of bits being bits that do not influence a value of a resulting first test output vector, and a second portion of the plurality of bits being bits that will influence the value of the first test output vector;

scanning out the first test output vectors from the first run of test patterns;

comparing the value of the first test output vectors to first expected values;

changing bit values of the first portion of the plurality of bits for each test pattern of the first run of test patterns to generate a second run of test patterns;

scanning in the second run of test patterns to the logic circuits on the integrated circuit device;

scanning out the second test output vectors resulting from the second run of test patterns; and

comparing a value of the second run of test patterns to second expected values.

10. The method of claim 9, wherein the first portion of the plurality of bits are characterized as being don'"'"'t care bits, and the second portion of the plurality of bits are characterized as being care bits.

11. The method of claim 9, wherein changing bit values further comprises using a pseudo random number generator to change the bit values.

12. The method of claim 9, wherein the method is for triggering a malicious hardware circuit undetected by production testing.

13. A method for triggering and detecting a malicious circuit on an integrated circuit device, the method comprising:

scanning in a first run of test patterns to logic circuits on the integrated circuit device using logic built-in self-test (LBIST), the first run of test patterns comprising a plurality of test patterns, each test pattern of the first run of test patterns comprising a plurality of bits, a first portion of the plurality of bits being bits that do not influence a value of a resulting first test output vector, and a second portion of the plurality of bits being bits that will influence the value of the first test output vector;

scanning out the first test output vectors from the first run of test patterns;

comparing the value of the first test output vectors to first expected values;

changing bit values of the first portion of the plurality of bits for each test pattern of the first run of test patterns to generate a second run of test patterns;

scanning in the second run of test patterns to the logic circuits on the integrated circuit device;

scanning out the second test output vectors resulting from the second run of test patterns;

comparing a value of the second run of test patterns to second expected values; and

detecting the malicious hardware in response to comparing the values of the first and second test output vectors.

14. The method of claim 13, wherein the first portion of the plurality of bits are characterized as being don'"'"'t care bits, and the second portion of the plurality of bits are characterized as being care bits.

15. The method of claim 13, wherein changing bit values further comprises using a pseudo random number generator to change the bit values.

16. The method of claim 13, wherein the logic circuits being tested are realized in a register-transfer level (RTL) design and implemented as registers and combinational logic on the integrated circuit device.