NEUROMORPHIC CIRCUIT HAVING 3D STACKED STRUCTURE AND SEMICONDUCTOR DEVICE HAVING THE SAME

• US 20190318230A1
• Filed: 11/15/2018
• Published: 10/17/2019
• Est. Priority Date: 04/17/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CHO, WOO-YEONG, O, SEONG-IL, YU, HAK-SOO, CHOI, MIN-SU
• Granted Patent: US 11,410,026 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 15/163 Interprocessor communication
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays

Abstract

Provided are a neuromorphic circuit having a three-dimensional stack structure and a semiconductor device including the neuromorphic circuit. The semiconductor device includes a first semiconductor layer including one or more synaptic cores, each synaptic core including neural circuits arranged to perform neuromorphic computation. A second semiconductor layer is stacked on the first semiconductor layer and includes an interconnect forming a physical transfer path between synaptic cores. A third semiconductor layer is stacked on the second semiconductor layer and includes one or more synaptic cores. At least one through electrode is formed, through which information is transferred between the first through third semiconductor layers. Information from a first synaptic core in the first semiconductor layer is transferred to a second synaptic core in the third semiconductor layer via the one of more through electrodes and an interconnect of the second semiconductor layer.

Claims

1. A semiconductor device comprising:

a first semiconductor layer comprising one or more synaptic cores, each synaptic core comprising neural circuits to perform neuromorphic computation;

a second semiconductor layer stacked on the first semiconductor layer and comprising an interconnect forming a physical transfer path between synaptic cores;

a third semiconductor layer stacked on the second semiconductor layer and comprising one or more synaptic cores; and

one or more through electrodes, through which information is transferred between the first through third semiconductor layers,

wherein information from a first synaptic core in the first semiconductor layer is transferred to a second synaptic core in the third semiconductor layer via the one or more through electrodes and the interconnect of the second semiconductor layer.

2. The semiconductor device of claim 1, wherein the through electrode is a through silicon via (TSV).

3. The semiconductor device of claim 1, wherein the second semiconductor layer further comprises a router for determining an information transfer path between the synaptic cores.

4. The semiconductor device of claim 1, wherein each of the first and third semiconductor layers further comprises a router for determining an information transfer path between the synaptic cores.

5. The semiconductor device of claim 1, wherein each synaptic core further comprises a local router for determining an information transfer path between the neural circuits and a local interconnect forming a physical information transfer path in each synaptic core.

6. The semiconductor device of claim 5, wherein the synaptic cores further comprise memristers for storing synapse information and performing weight computation by using the synapse information.

7. The semiconductor device of claim 1, wherein the neuromorphic computation comprises a computation of nodes having a plurality of layer structures, and a computation result of first nodes belonging to a first layer from among the nodes is provided to second nodes belonging to a second layer,

wherein the first nodes are included in a first synaptic core of the first semiconductor layer, and the second nodes are included in a second synaptic core of the third semiconductor layer.

8. The semiconductor device of claim 1, wherein first information from a first synaptic core in the first semiconductor layer is transferred to a second synaptic core in the third semiconductor layer through the interconnect of the second semiconductor layer, and

second information from the first synaptic core in the first semiconductor layer is transferred to a third synaptic core in the first semiconductor layer through an interconnect of the second semiconductor layer.

9. The semiconductor device of claim 1, wherein the semiconductor device comprises N semiconductor layers including the first through third semiconductor layers, where N is an integer greater than 3, and

wherein the N semiconductor layers are implemented such that semiconductor layers each including a synaptic core, and semiconductor layers each including an interconnect, are alternately stacked.

10. The semiconductor device of claim 1, wherein the one or more through electrodes is formed within at least one of the first, second or third semiconductor layers.

11. A neuromorphic circuit comprising:

a synaptic core layer comprising a plurality of synaptic cores, each synaptic core comprising a plurality of neural circuits and a memory array storing synapse information;

global routers each configured to determine an information transfer path between the synaptic cores; and

a global interconnect layer forming a physical transfer path between the global routers,

wherein the synaptic core layer and the global interconnect layer are arranged in a stack structure, and information from a synaptic core of the synaptic core layer is transferred to the global interconnect layer via one or more through electrodes.

12. The neuromorphic circuit of claim 11, wherein the through electrode is a through silicon via (TSV).

13. The neuromorphic circuit of claim 11, wherein the global routers are integrated in the synaptic core layer with the synaptic cores.

14. The neuromorphic circuit of claim 11, wherein the global routers are integrated in the global interconnect layer along with a global interconnect.

15. The neuromorphic circuit of claim 14, wherein the neuromorphic circuit comprises first through Nth semiconductor layers (where N is an integer greater than 2) including the synaptic core layer and the global interconnect layer, the first semiconductor layer is the synaptic core layer, and the second semiconductor layer is the global interconnect layer, and

the first through Nth semiconductor layers are implemented such that synaptic core and global interconnect layers thereof are alternately stacked.

16. The neuromorphic circuit of claim 11, wherein each of the synaptic cores comprises a local router determining an information transfer path between the neural circuits and a local interconnect forming a physical information transfer path in each of the synaptic cores.

17. The neuromorphic circuit of claim 16, wherein the synaptic core layer comprises first through third semiconductor layers that have a stacked structure and communicate with each other via through electrodes,

wherein some of a plurality of neural circuits of any one synaptic core are formed in the first semiconductor layer, the local interconnect is formed in the second semiconductor layer stacked on the first semiconductor layer, and other ones of the plurality of neural circuits are formed in the third semiconductor layer.

18. The neuromorphic circuit of claim 17, wherein the local router is formed in the second semiconductor layer along with the local interconnect.

19. The neuromorphic circuit of claim 17, wherein the local router is formed in the first semiconductor layer and the third semiconductor layer along with the neural circuits.

20. The neuromorphic circuit of claim 11, wherein the memory array comprises memristers.

21. The neuromorphic circuit of claim 11, wherein the one or more through electrodes is formed within at least one of the synaptic core layer or the global interconnect layer.

22. An operating method of a semiconductor device, wherein the semiconductor device comprises a plurality of semiconductor layers with circuitry communicating with each other via a through silicon via (TSV), the operating method comprising:

transferring information from a first synaptic core including a plurality of neural circuits formed in a first semiconductor layer to a first router associated with the first synaptic core;

transferring the information from the first router to a second router via an interconnect formed in a second semiconductor layer stacked on the first semiconductor layer; and

transferring the information from the second router to a second synaptic core formed in a third semiconductor layer stacked on the second semiconductor layer, the second synaptic core being associated with the second router.

23. The operating method of claim 22, wherein the information is a result of neuromorphic computation performed using the neural circuits with respect to input information provided to the first synaptic circuit.

24. The operating method of claim 22, wherein the information is first information, and the operating method further comprising:

transferring second information from the first synaptic core to a third router through an interconnect of the second semiconductor layer; and

transferring the second information to a third synaptic core formed in the first semiconductor layer and arranged to correspond to the third router.

25. The operating method of claim 22, wherein path information for determining a transfer path of the information is further transferred from the first synaptic core to the first router,

wherein the information is selectively transferred to the first semiconductor layer or the third semiconductor layer based on the path information.

26. The operating method of claim 22, wherein the first router and the second router are formed in the second semiconductor layer.

27. The operating method of claim 22, wherein the first router is formed in the first semiconductor layer, and the second router is formed in the third semiconductor layer.

28. A semiconductor device comprising:

a first semiconductor layer comprising processing elements of a parallel processing system;

a second semiconductor layer stacked on the first semiconductor layer and comprising an interconnect forming a physical transfer path between processing elements;

a third semiconductor layer stacked on the second semiconductor layer and comprising processing elements; and

one or more through electrodes disposed within at least one of the first, second and third layers, through which information is transferred between the first through third semiconductor layers,

wherein information from a first processing element in the first semiconductor layer is transferred to a second processing element in the third semiconductor layer via the one or more through electrodes and the interconnect of the second semiconductor layer.

29. The semiconductor device of claim 28, wherein the at least one through electrode extends continuously from the first semiconductor layer to the third semiconductor layer.

30. The semiconductor device of claim 28, further comprising a plurality of routers, each associated with one of the processing elements and each for determining an information transfer path between the associated processing element and another one of the processing elements.