SAMPLING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE USING A SAMPLING CIRCUIT

• US 20190318772A1
• Filed: 11/13/2018
• Published: 10/17/2019
• Est. Priority Date: 04/16/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: KIM, Bo Ram, KWON, Dae Han
• Granted Patent: US 10,600,457 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A sampling circuit may include a first timing determination circuit, a second timing determination circuit, and a sampling data output circuit. The first timing determination circuit may determine a first timing of sampling data in response to a first sampling timing signal. The second timing determination circuit may determine a second timing of the sampling data in response to a second sampling timing signal. The sampling data output circuit may output the sampling data having effective data values of the data between the first timing and the second timing in response to outputs from the first and second timing determination circuits.

Claims

1. A sampling circuit comprising:

a first timing determination circuit for determining a first timing of sampling data in response to a first sampling timing signal;

a second timing determination circuit for determining a second timing of the sampling data in response to a second sampling timing signal; and

a sampling data output circuit for outputting the sampling data having effective data values of the sampling data between the first timing and the second timing in response to output signals from the first and second timing determination circuits.

2. The sampling circuit of claim 1, wherein there is a phase difference between the first and second sampling timing signals.

3. The sampling circuit of claim 2, wherein the phase difference between the first and second sampling timing signals is substantially ninety degrees (90°

).

4. The sampling circuit of claim 2, wherein the first and second sampling timing signals comprise at least one of a clock signal and a data strobe signal.

5. The sampling circuit of claim 1, wherein the first timing determination circuit outputs data at a rising timing of the first sampling timing signal.

6. The sampling circuit of claim 1, wherein the second timing determination circuit inverts and outputs the second sampling timing signal.

7. The sampling circuit of claim 1, wherein the sampling data output circuit outputs an output signal from the first timing determination circuit as the sampling data until an output signal from the second timing determination circuit falls.

8. A sampling circuit for outputting data as sampling data during an interval between a rising timing of a first sampling timing signal and a rising timing of a second sampling timing signal.

9. The sampling circuit of claim 8, wherein the sampling circuit comprises:

a first timing determination circuit for outputting the data at a rising timing of the first sampling timing signal;

a second timing determination circuit for inverting and outputting the second sampling timing signal; and

a sampling data output circuit for outputting an output signal from the first timing determination circuit as the sampling data until an output signal from the second timing determination circuit falls.

10. A semiconductor memory device comprising:

a plurality of sampling circuits for outputting memory output data as sampling data in response to rising timings of at least two different sampling timing signals; and

a data arrangement circuit for arranging the sampling data and for outputting arrangement data.

11. The semiconductor memory device of claim 10, wherein the memory output data correspond to parallel data and the arrangement data correspond to serial data.

12. The semiconductor memory device of claim 10, wherein each of the sampling circuits outputs the memory output data as the sampling data during an interval corresponding to a phase difference between the sampling timing signals.

13. The semiconductor memory device of claim 12, wherein each of the sampling circuits outputs the memory output data as the sampling data during an interval between rising timings of the sampling timing signals.

14. The semiconductor memory device of claim 13, wherein each of the sampling circuits comprises:

a first timing determination circuit for receiving any one of the sampling timing signals and the memory output data;

a second timing determination circuit for inverting and outputting the rest of the sampling timing signals except for the sampling timing signal inputted into the first timing determination circuit; and

a sampling data output circuit for outputting the sampling data in response to output signals from the first and second timing determination circuits.

15. The semiconductor memory device of claim 14, wherein each of the first and second timing determination circuits comprise at least one inverter.

16. The semiconductor memory device of claim 15, wherein the inverter of the first timing determination circuit controls a rising edge slope of the output signal from the first timing determination circuit in response to an enable signal.

17. The semiconductor memory device of claim 15, wherein the inverter of the second timing determination circuit controls a falling edge slope of the output signal from the second timing determination circuit in response to an enable signal.