SYSTEMS, METHODS, AND APPARATUS FOR MEMORY CELLS WITH COMMON SOURCE LINES
First Claim
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1. A system comprising:
- a processor;
at least one voltage source; and
a memory array;
wherein;
the processor is configured to provide control signals to the at least one voltage source and the memory array;
the at least one voltage source is configured to generate a plurality of voltages, wherein the plurality of voltages comprises at least one voltage of at least 3.5V; and
the memory array comprises;
a first memory cell comprising a first transistor coupled to a second transistor, wherein the first transistor comprises a memory element; and
a second memory cell comprising a third transistor coupled to a fourth transistor;
wherein, in response to an initiation of a programming operation, the memory array receives at least one of the plurality voltages at each of a drain of the first transistor, a drain of the third transistor, a gate of the second transistor, a gate of the fourth transistor, and a gate of the first transistor, andwherein receiving the voltages results in a change in one or more electrical characteristics of the memory element.
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Abstract
A method for operating a memory device includes the steps of providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, providing a second voltage to a gate of a second transistor of the first memory cell and a gate of a fourth transistor of the second memory cell, and providing a third voltage to a gate of the first transistor of the first memory cell and a gate of the third transistor of the second memory cell. Other embodiments are also described.
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5 Claims
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1. A system comprising:
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a processor; at least one voltage source; and a memory array; wherein; the processor is configured to provide control signals to the at least one voltage source and the memory array; the at least one voltage source is configured to generate a plurality of voltages, wherein the plurality of voltages comprises at least one voltage of at least 3.5V; and the memory array comprises; a first memory cell comprising a first transistor coupled to a second transistor, wherein the first transistor comprises a memory element; and a second memory cell comprising a third transistor coupled to a fourth transistor; wherein, in response to an initiation of a programming operation, the memory array receives at least one of the plurality voltages at each of a drain of the first transistor, a drain of the third transistor, a gate of the second transistor, a gate of the fourth transistor, and a gate of the first transistor, and wherein receiving the voltages results in a change in one or more electrical characteristics of the memory element. - View Dependent Claims (2, 3, 4, 5)
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Specification