CIRCUIT FOR REGULATING LEAKAGE CURRENT IN CHARGE PUMP

• US 20190318790A1
• Filed: 12/19/2018
• Published: 10/17/2019
• Est. Priority Date: 04/12/2018
• Status: Active Grant

• Current Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
• Original Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
• Inventors: TANG, Yuan, SHENG, Bin, CHA, Byoung Kwon, XU, Yi, HSU, Jen-Tai
• Granted Patent: US 10,606,299 B2
• Time in Patent Office: Days
• CPC Class Codes: G05F 3/02 Regulating voltage or current
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A circuit for regulating a leakage current in a charge pump is disclosed. The circuit includes a bias voltage generating circuit and a first transistor, wherein: the bias voltage generating circuit generates a bias voltage that is proportional to a supply voltage; a gate of the first transistor is coupled to the bias voltage; the first transistor has a drain that is coupled to an output of the charge pump and a source that is grounded; a voltage the drain of the first transistor is proportional to the supply voltage; and a current flowing through the source and drain of the first transistor is proportional to the supply voltage that powers the charge pump.

Claims

1. A circuit for regulating a leakage current in a charge pump, comprising a bias voltage generating circuit and a first transistor, wherein:

the bias voltage generating circuit generates a bias voltage that is proportional to a supply voltage;

the first transistor has a gate coupled to the bias voltage and a source that is grounded;

the first transistor has a drain coupled to an output of the charge pump, a voltage at the drain of the first transistor being proportional to the supply voltage; and

a current between the source and drain of the first transistor is proportional to the supply voltage that powers the charge pump.

2. The circuit of claim 1, wherein the first transistor is an N-channel field-effect transistor.

3. The circuit of claim 1, further comprising a second transistor,

the second transistor having a gate coupled to the supply voltage, a source connected to the drain of the first transistor and a drain connected to the output of the charge pump.

4. The circuit of claim 3, wherein the second transistor is an N-channel field-effect transistor.

5. The circuit of claim 3, wherein a breakdown voltage between the source and drain of the second transistor is higher than a breakdown voltage between the source and drain of the first transistor.

6. The circuit of claim 1, wherein the bias voltage generating circuit comprises a third transistor and a fourth transistor, wherein:

the third transistor has a gate that is grounded, a source coupled to the supply voltage and a drain connected to a drain of the fourth transistor; and

the fourth transistor has a gate connected both to the drain of the fourth transistor and the gate of the first transistor and a source that is grounded.

7. The circuit of claim 6, wherein the third transistor is a P-channel field-effect transistor and the fourth transistor is an N-channel field-effect transistor.

8. The circuit of claim 6, wherein the gate of the first transistor is connected to the drains of the third and fourth transistors.

9. The circuit of claim 1, wherein the voltage at the drain of the first transistor is equal to the supply voltage minus a threshold voltage of the first transistor.

10. The circuit of claim 1, wherein the supply voltage ranges from 1.6 V to 3.9 V.

11. The circuit of claim 1, wherein a current flowing through the source and drain of the first transistor ranges from 10 μ

A to 70 μ

A.

12. A circuit for regulating a leakage current in a charge pump, comprising a first transistor, a third transistor and a fourth transistor, wherein:

the first transistor has a gate connected to drains of the third and fourth transistors for receiving a bias voltage that is proportional to a supply voltage;

the first transistor has a drain coupled to an output of the charge pump and a source that is grounded, a voltage at the drain of the first transistor being proportional to the supply voltage;

the third transistor has a gate that is grounded, a source coupled to the supply voltage and the drain connected to the drain of the fourth transistor;

the fourth transistor has a gate connected both to the drain of the fourth transistor and the gate of the first transistor and a source that is grounded; and

a current between the source and drain of the first transistor is proportional to the supply voltage that powers the charge pump.

13. The circuit of claim 12, wherein the first transistor is an N-channel field-effect transistor, the third transistor is a P-channel field-effect transistor and the fourth transistor is an N-channel field-effect transistor.

14. The circuit of claim 12, further comprising a second transistor,

the second transistor having a gate coupled to the supply voltage, a source connected to the drain of the first transistor and a drain connected to the output of the charge pump.

15. The circuit of claim 14, wherein the second transistor is an N-channel field-effect transistor.

16. The circuit of claim 14, wherein a breakdown voltage between the source and drain of the second transistor is higher than a breakdown voltage between the source and drain of the first transistor.

17. The circuit of claim 12, wherein the voltage at the drain of the first transistor is equal to the supply voltage minus a threshold voltage of the first transistor.

18. The circuit of claim 12, wherein the supply voltage ranges from 1.6 V to 3.9 V.

19. The circuit of claim 12, wherein a current flowing through the source and drain of the first transistor ranges from 10 μ

A to 70 μ

A.