METHODS OF PROTECTING STRUCTURE OF INTEGRATED CIRCUIT FROM REWORK

• US 20190318927A1
• Filed: 04/16/2018
• Published: 10/17/2019
• Est. Priority Date: 04/16/2018
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Sun, Lei, Zhang, Xunyuan, Mont, Frank W., Law, Shao Beng
• Granted Patent: US 10,636,656 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288

Abstract

The present disclosure relates to methods of protecting a structure of an integrated circuit (IC) from rework, and more particularly, to methods of protecting a structure of an IC without impacting the critical dimension or the profile of the structure. For example, a method of protecting a structure of an IC from rework may include forming a first layer on a second layer; forming one or more first openings in the first layer, the first openings exposing a top surface of the second layer; selectively growing a Group VIII metal within the one or more first openings, thereby forming one or more first plugs; forming one or more final openings in the first layer; and removing the one or more first plugs.

Claims

1. A method of protecting an opening profile of an integrated circuit from rework, the method comprising:

forming a first layer on a second layer, at least one of the first and second layers being a metal-containing layer;

forming one or more first openings in the first layer, the one or more first openings defining the opening profile of the integrated circuit and exposing a top surface of the second layer;

selectively growing a Group VIII metal within the one or more first openings, thereby forming one or more first plugs;

forming one or more final openings in the first layer while the one or more first openings in the first layer are protected by the one or more first plugs; and

removing the one or more first plugs.

2. The method of claim 1, wherein the first layer is the metal-containing layer and the growing of the Group VIII metal comprises selectively growing the Group VIII metal on exposed sidewalls of the first openings of the metal-containing layer.

3. The method of claim 2, wherein the metal-containing layer is a titanium nitride (TiN) layer.

4. The method of claim 2, wherein the Group VIII metal is cobalt (Co) or ruthenium (Ru).

5. The method of claim 2, wherein the second layer is a low-temperature oxide (LTO) layer.

6. The method of claim 2, wherein a profile of the one or more first openings is unchanged by the forming of the one or more final openings.

7. The method of claim 2, further comprising, after the forming of the first plugs and before the forming of the final openings:

forming one or more second openings in the first layer, the second openings exposing the top surface of the second layer and further defining the opening profile, the one or more first openings in the first layer and the opening profile being protected by the one or more first plugs; and

selectively growing the Group VIII metal on exposed sidewalls of the second openings of the metal-containing layer, thereby forming one or more second plugs,

wherein the removing the one or more first plugs also includes removing the one or more second plugs.

8. The method of claim 7, wherein the first and second openings are via openings and the forming of the first and second via openings comprises:

forming an over-layer stack on the first layer, the over-layer stack comprising a resist layer having one or more resist openings;

forming via openings through the first layer at the one or more resist openings such that the top surface of the second layer is exposed; and

removing the over-layer stack.

9. The method of claim 7, wherein a profile of the one or more first openings is unchanged by the forming of the one or more second openings and the one or more final openings, and a profile of the one or more second openings is unchanged by the forming of the one or more final openings.

10. The method of claim 1, wherein the second layer is the metal-containing layer and the growing of the Group VIII metal comprises selectively growing the Group VIII metal on the exposed top surface of the second layer within the first openings of the first layer.

11. The method of claim 10, wherein the metal-containing layer is a titanium nitride (TiN) layer.

12. The method of claim 10, wherein the Group VIII metal is cobalt (Co) or ruthenium (Ru).

13. The method of claim 10, wherein the first layer is a silicon dioxide (SiO₂) precursor layer.

14. The method of claim 13, wherein the SiO₂ precursor layer comprises tetraethyl orthosilicate (TEOS).

15. The method of claim 10, wherein a profile of the one or more first openings is unchanged by the forming of the one or more final openings.

16. The method of claim 10, further comprising, after the forming of the first plugs and before the forming of the final openings:

forming one or more second openings in the first layer, the second openings exposing the top surface of the second layer, the one or more first openings in the first layer and the opening profile being protected by the one or more first plugs; and

selectively growing the Group VIII metal on the exposed top surface of the second layer within the second openings of the first layer, thereby forming one or more second plugs.

17. The method of claim 16, wherein the first and second openings are line trenches and the forming of the first and second line trenches comprises:

forming an over-layer stack on the first layer, the over-layer stack comprising a resist layer having one or more resist openings;

forming line trenches through the first layer at the one or more resist openings such that the top surface of the second layer is exposed; and

removing the over-layer stack.

18. The method of claim 16, wherein a profile of the one or more first openings is unchanged by the forming of the one or more second openings and the one or more final openings, and a profile of the one or more second openings is unchanged by the forming of the one or more final openings.

19. A method of protecting an opening profile of an integrated circuit from rework, the method comprising:

forming a first layer on a second layer, the first or second layer being a titanium nitride (TiN) layer;

forming an over-layer stack on the first layer, the over-layer stack comprising a resist layer having one or more resist openings;

forming one or more first openings through the first layer at the one or more resist openings, the one or more first openings defining the opening profile of the integrated circuit, and exposing the top surface of the second layer;

removing at least a portion of the over-layer stack;

selectively growing cobalt (Co) or ruthenium (Ru) within the one or more first openings, thereby forming one or more first plugs;

removing any remaining portion of the over-layer stack;

forming one or more final openings in the first layer in the first layer while the one or more first openings in the first layer are protected by the one or more first plugs; and

removing the one or more first plugs.

20. The method of claim 19, wherein the second layer is formed over an under-layer stack, the under-layer stack comprising one or more layers of the integrated circuit, one or more stacks of layers of the integrated circuit, or a combination thereof.