SPACER IMAGE TRANSFER WITH DOUBLE MANDREL

• US 20190318928A1
• Filed: 04/12/2018
• Published: 10/17/2019
• Est. Priority Date: 04/12/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mignot, Yann, Xu, Yongan
• Granted Patent: US 10,629,436 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0276 using an anti-reflective coating anti-reflective coating for lithography in general G03F7/09
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

A method for providing an etch mask for microelectronic processing that includes forming a material stack on a surface to be etched, wherein the material stack of at least a first material layer atop the surface to be etched for a base mandrel layer, and a second material layer atop the first material layer to provide a cap mandrel layer. If a following step, the material stack may be patterned and etched to provide double mandrel structures each including said base mandrel layer and said cap mandrel layer. A sidewall spacer is formed on sidewalls of the double mandrel structures.

Claims

1. A patterning method for microelectronic devices comprising:

forming a material stack on a surface to be etched, wherein the material stack of at least a first material layer atop the surface to be etched for a base mandrel layer, and a second material layer atop the first material layer to provide a cap mandrel layer;

patterning the material stack to provide double mandrel structures each including said base mandrel layer and said cap mandrel layer; and

forming a sidewall spacer on sidewalls of the double mandrel structures.

2. The method of claim 1, wherein the base mandrel layer comprises a Ti containing material.

3. The method of claim 1, wherein the cap mandrel layer comprises an amorphous silicon containing material.

4. The method of claim 1, wherein said forming the sidewall spacer comprises:

depositing a spacer material layer using a conformal deposition process; and

etching the spacer material layer with an anisotropic etch process to remove horizontally orientated portions of the spacer material layer, wherein vertically orientated portions of the spacer material layer remain to provide the sidewall spacer.

5. The method of claim 1 further comprising etching the surface to be etched in a non-mandrel portion of a mask provided by the double mandrel structures and the sidewall spacer.

6. The method of claim 5, further comprising etching the surface to be etched in a mandrel portion of a mask provided by the sidewall spacers following removing the cap mandrel layer and the base mandrel layer of the double mandrel structures.

7. The method of claim 5, wherein the etching using the non-mandrel portion of the mask is conducted before the etching using the mandrel portion of the mask.

8. The method of claim 7, wherein the etching using the non-mandrel portion of the mask is conducted after the etching using the mandrel portion of the mask.

9. The method of claim 1, wherein the sidewall spacer present on sidewalls of the double mandrel structure is a first sidewall spacer, wherein the method further comprises:

removing the cap mandrel layer selectively to the base mandrel layer;

forming second sidewall spacers on inner and outer sidewalls of the first sidewall spacer;

removing the first sidewall spacer; and

etching the surface to be etched using a mask provided by the second sidewall spacers and the base dielectric layer of the double mandrel structures.

10. A patterning method for microelectronic devices comprising:

forming a material stack on a surface to be etched, wherein the material stack of at least a first material layer atop dielectric layers to be etched for a base mandrel layer, and a second material layer atop the first material layer to provide a cap mandrel layer;

patterning the material stack to provide double mandrel structures each including said base mandrel layer and said cap mandrel layer;

forming a sidewall spacer on sidewalls of the double mandrel structures;

etching trenches in the dielectric layers using the double mandrel structures and sidewall spacers; and

filling the trenches with an electrically conductive material to provide metal lines.

11. The method of claim 10, wherein said forming the sidewall spacer comprises:

depositing a spacer material layer using a conformal deposition process; and

etching the spacer material layer with an anisotropic etch process to remove horizontally orientated portions of the spacer material layer, wherein vertically orientated portions of the spacer material layer remain to provide the sidewall spacer.

12. The method of claim 10, wherein said trenches are etched in the dielectric layers using a non-mandrel portion of the mask provided by the double mandrel structures and the sidewall spacer.

13. The method of claim 10, wherein said trenches are etched in the dielectric layers using a mandrel portion of a mask provided by the sidewall spacers following removing the cap mandrel layer and the base mandrel layer of the double mandrel structures.

14. The method of claim 13, wherein the etching using the non-mandrel portion of the mask is conducted before the etching using the mandrel portion of the mask, or the etching using the non-mandrel portion of the mask is conducted after the etching using the mandrel portion of the mask.

15. The method of claim 10, wherein the sidewall spacer present on sidewalls of the double mandrel structure is a first sidewall spacer, wherein the method further comprises:

removing the cap mandrel layer selectively to the base mandrel layer;

forming second sidewall spacers on inner and outer sidewalls of the first sidewall spacer;

removing the first sidewall spacer; and

etching the dielectric layers using a mask provided by the second sidewall spacers and the base dielectric layer of the double mandrel structures.

16. A patterning method for microelectronic devices comprising:

forming a material stack on a surface to be etched, wherein the material stack of at least a first material layer atop semiconductor layers to be etched for a base mandrel layer, and a second material layer atop the first material layer to provide a cap mandrel layer;

patterning the material stack to provide double mandrel structures each including said base mandrel layer and said cap mandrel layer;

forming a sidewall spacer on sidewalls of the double mandrel structures; and

etching fins in the semiconductors layers using the double mandrel structures and sidewall spacers.

17. The method of claim 16, wherein said fins are etched in the semiconductor layers using a non-mandrel portion of the mask provided by the double mandrel structures and the sidewall spacer.

18. The method of claim 16, wherein said fins are etched in the semiconductor layers using a mandrel portion of a mask provided by the sidewall spacers following removing the cap mandrel layer and the base mandrel layer of the double mandrel structures.

19. The method of claim 16, wherein the etching using the non-mandrel portion of the mask is conducted before the etching using the mandrel portion of the mask, or the etching using the non-mandrel portion of the mask is conducted after the etching using the mandrel portion of the mask.

20. The method of claim 16, wherein the sidewall spacer present on sidewalls of the double mandrel structure is a first sidewall spacer, wherein the method further comprises:

removing the cap mandrel layer selectively to the base mandrel layer;

forming second sidewall spacers on inner and outer sidewalls of the first sidewall spacer;

removing the first sidewall spacer; and

etching the semiconductor layers using a mask provided by the second sidewall spacers and the base dielectric layer of the double mandrel structures.