MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

• US 20190318939A1
• Filed: 06/26/2019
• Published: 10/17/2019
• Est. Priority Date: 03/21/2017
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: HASHIZUME, Shoji, Takada, Keita
• Granted Patent: US 10,811,281 B2
• Time in Patent Office: Days
• CPC Class Codes: B29C 2045/0027 Gate or gate mark locations
• CPC Class Codes: B29C 45/0025 Preventing defects on the moulded article, e.g. weld lines, shrinkage marks preventing defects on the preformed parts or layers B29C45/14836
• CPC Class Codes: B29C 45/0046 Details relating to the filling pattern or flow paths or flow characteristics of moulding material in the mould cavity
• CPC Class Codes: B29C 45/14336 Coating a portion of the article, e.g. the edge of the article B29C45/14573 and B29C45/14598 take precedence
• CPC Class Codes: B29C 45/14655 connected to or mounted on a carrier, e.g. lead frame
• CPC Class Codes: B29L 2031/34 Electrical apparatus, e.g. sparking plugs or parts thereof
• CPC Class Codes: H01L 21/4825 Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
• CPC Class Codes: H01L 21/4842 Mechanical treatment, e.g. punching, cutting, deforming, cold welding
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2223/54406 comprising alphanumeric information
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49503 : characterised by the die pad
• CPC Class Codes: H01L 23/49513 : having bonding material between chip and die pad
• CPC Class Codes: H01L 23/4952 : the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 : Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H02P 27/06 : using dc to ac converters or inverters H02P27/05 takes precedence

Abstract

A manufacturing method of a semiconductor device, includes: (a) preparing a lead frame having: a first tie bar extending in a first direction in plan view so as to couple a plurality of first leads to one another; a second tie bar extending in the first direction in plan view so as to couple a plurality of second leads to one another; a coupling portion coupled to the first tie bar and the second tie bar; a first chip mounting portion arranged between the first tie bar and the second tie bar in plan view; and a second chip mounting portion arranged between the first chip mounting portion and the second tie bar in plan view; and (b) after the (a), mounting a first semiconductor chip on the first chip mounting portion and mounting a second semiconductor chip on the second chip mounting portion.

Claims

1. A manufacturing method of a semiconductor device, comprising:

(a) preparing a lead frame having;

a first tie bar extending in a first direction in plan view so as to couple a plurality of first leads to one another;

a second tie bar extending in the first direction in plan view so as to couple a plurality of second leads to one another;

a coupling portion coupled to the first tie bar and the second tie bar;

a first chip mounting portion arranged between the first tie bar and the second tie bar in plan view; and

a second chip mounting portion arranged between the first chip mounting portion and the second tie bar in plan view;

(b) after the (a), mounting a first semiconductor chip on the first chip mounting portion and mounting a second semiconductor chip on the second chip mounting portion; and

(c) after the (b), sandwiching the lead frame, on which the first semiconductor chip and the second semiconductor chip are mounted, between a first mold and a second mold, and then supplying resin into a cavity defined by the first mold and the second mold via a gate portion that is formed on the first mold and is provided at a position overlapping the coupling portion of the lead frame to form an encapsulation body that encapsulates a portion of each of the first leads, a portion of each of the second leads, the first chip mounting portion, the second chip mounting portion, the first semiconductor chip, and the second semiconductor chip,

wherein the plurality of first leads each include an inner lead portion covered by the encapsulation body and an outer lead portion exposed to the outside of the encapsulation body,

the plurality of first leads include;

a third lead having the inner lead portion located between the first tie bar and the first chip mounting portion in a second direction orthogonal to the first direction; and

a fourth lead having the inner lead portion not located between the first tie bar and the first chip mounting portion,

in plan view, the first chip mounting portion includes;

a first side extending along the first tie bar;

a second side opposite to the first side;

a third side extending along the second direction; and

a fourth side opposite to the third side and extending along the second direction,

in plan view, the first side of the first chip mounting portion is located between the first tie bar and the second side of the first chip mounting portion,

a distance in the second direction from the first side of the first chip mounting portion to a first virtual line extending in the first direction and passing through a midpoint of the first tie bar and the second tie bar in the second direction is greater than a length of the inner lead portion of the third lead in the second direction,

a length of the inner lead portion of the fourth lead in the second direction is greater than the length of the inner lead portion of the third lead in the second direction,

in the (c), when the lead frame is sandwiched between the first mold and the second mold, the gate portion of the first mold is located closer to the first tie bar than to the second tie bar in plan view,

in the (c), when the lead frame is sandwiched between the first mold and the second mold, a portion of the inner lead portion of the fourth lead is located between the first chip mounting portion and the gate portion in plan view,

in the (c), when the lead frame is sandwiched between the first mold and the second mold, a spacing between the portion of the inner lead portion of the fourth lead and the gate portion in the first direction is smaller than a spacing between the portion of the inner lead portion of the fourth lead and the first chip mounting portion in the first direction, and

in the (c), the resin is supplied into the cavity with the lead frame sandwiched between the first mold and the second mold such that the portion of the inner lead portion of the fourth lead is located on a second virtual line passing through the gate portion and extending in the first direction in plan view.

2. The manufacturing method of a semiconductor device according to claim 1, further comprising:

(d) after the (c), removing the lead frame, on which the encapsulation body is formed, from between the first mold and the second mold, and then separating a gate resin located at the gate portion of the first mold and coupled to the encapsulation body from the encapsulation body,

wherein the encapsulation body includes a main surface and a back surface opposite to the main surface,

in plan view, the main surface includes;

a fifth side extending along the first direction;

a sixth side opposite to the fifth side;

a seventh side extending along the second direction; and

an eighth side opposite to the seventh side,

the encapsulation body further includes;

a first side surface attaching the fifth side to the back surface;

a second side surface attaching the sixth side to the back surface;

a third side surface attaching the seventh side to the back surface; and

a fourth side surface attaching the eighth side to the back surface, and

the third side surface includes a resin injection trace located so as to correspond to the gate portion.

3. The manufacturing method of a semiconductor device according to claim 2,

wherein a thickness of the resin injection trace in a third direction from the main surface to the back surface is less than a length from the seventh side to the fourth lead in the first direction.

4. The manufacturing method of a semiconductor device according to claim 1,

wherein in the (b),

the first semiconductor chip includes a plurality of first pad electrodes,

the second semiconductor chip includes a plurality of second pad electrodes,

the number of first pad electrodes is less than the number of second pad electrodes, and

a plane area of the first semiconductor chip is smaller than a plane area of the second semiconductor chip.

5. The manufacturing method of a semiconductor device according to claim 1,

wherein the length of the inner lead portion of the fourth lead in the second direction is greater than the distance from the first virtual line to the first side of the first mounting portion in the second direction.

6. The manufacturing method of a semiconductor device according to claim 1,

wherein the fourth lead is not electrically connected with either the first semiconductor chip or the second semiconductor chip.

7. The manufacturing method of a semiconductor device according to claim 1,

wherein the plurality of first leads include a fifth lead having the inner lead portion not located between the first tie bar and the first chip mounting portion,

in plan view, the third lead is located between the fourth lead and the fifth lead, and

a length of the inner lead portion of the fifth lead in the second direction is less than a length of the inner lead portion of the fourth lead in the second direction.

8. The manufacturing method of a semiconductor device according to claim 1,

wherein the plurality of first leads include a sixth lead having the inner lead portion not located between the first tie bar and the first chip mounting portion in the second direction,

in plan view, the sixth lead is located between the third lead and the fourth lead, and

the inner lead portion of the sixth lead and the inner lead portion of the fourth lead are connected to each other.