SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

• US 20190318956A1
• Filed: 02/14/2019
• Published: 10/17/2019
• Est. Priority Date: 04/11/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CHOI, Hoon-Sung
• Granted Patent: US 10,832,939 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits

Abstract

A semiconductor comprises two transistors of the first conductivity type separated from two transistors of a second conductivity type by a first element isolation layer. Further, the two transistors of the first conductivity type are separated from each other by a second element isolation layer and the two transistors of the second conductivity type are separated from each other by a third element isolation layer. In example embodiments, the second and third element isolation layers are shallower than the first element isolation layer.

Claims

1. A semiconductor device comprising:

a substrate;

a first impurity region of a first conductivity type on the substrate;

a second impurity region of a second conductivity type on the substrate to be adjacent to the first impurity region;

a first semiconductor layer of the second conductivity type on the first impurity region;

a second semiconductor layer of the first conductivity type on the second impurity region;

a first buried insulation layer on the first semiconductor layer;

a second buried insulation layer on the second semiconductor layer;

a third semiconductor layer on the first buried insulation layer;

a fourth semiconductor layer on the second buried insulation layer;

a first transistor and a second transistor on the first semiconductor layer, respectively;

a third transistor on the second semiconductor layer;

a first element isolation layer which separates the second transistor and the third transistor; and

a second element isolation layer which separates the first transistor and the second transistor and is shallower than the first element isolation layer.

2. The semiconductor device of claim 1, further comprising:

a fourth transistor on the second semiconductor layer; and

a third element isolation layer, shallower than the first element isolation layer, which separates the fourth transistor and the third transistor.

3. The semiconductor device of claim 2, wherein the third element isolation layer is in the fourth semiconductor layer.

4. The semiconductor device of claim 1, wherein the first element isolation layer completely separates the first semiconductor layer and the second semiconductor layer.

5. The semiconductor device of claim 1, wherein the first impurity region and the second impurity region are partially in contact with each other.

6. The semiconductor device of claim 1, wherein the second element isolation layer is in the third semiconductor layer.

7. The semiconductor device of claim 1, further comprising:

a first well contact on the first semiconductor layer exposed by the third semiconductor layer and the first buried insulation layer.

8. The semiconductor device of claim 7, further comprising:

a second well contact on the second semiconductor layer exposed by the fourth semiconductor layer and the second buried insulation layer.

9. The semiconductor device of claim 1, wherein a capacitor is formed, using the first semiconductor layer and the third semiconductor layer as electrodes and using the first buried insulation layer as a dielectric.

10. The semiconductor device of claim 1, wherein the second element isolation layer is not between the first impurity region and the second impurity region.

11. The semiconductor device of claim 1, wherein the first transistor includes a first source/drain region,

the second transistor includes a second source/drain region, and

the second element isolation layer is between the first source/drain region and the second source/drain region.

12. The semiconductor device of claim 1, wherein the third semiconductor layer has the first conductivity type and the fourth semiconductor layer has the second conductivity type.

13. The semiconductor device of claim 1, wherein the third semiconductor layer has the second conductivity type and the fourth semiconductor layer has the first conductivity type.

14. A semiconductor device comprising:

a substrate;

a first impurity region of a first conductivity type and a second impurity region of a second conductivity type in contact with each other on the substrate;

a first semiconductor layer of the second conductivity type on the first impurity region;

a second semiconductor layer of the first conductivity type on the second impurity region;

a buried insulation layer on the first semiconductor layer and the second semiconductor layer;

a third semiconductor layer overlapping the first semiconductor layer, and a fourth semiconductor layer overlapping the second semiconductor layer on the buried insulation layer;

a first element isolation layer in the third semiconductor layer; and

a second element isolation layer which completely separates the first semiconductor layer and the second semiconductor layer.

15. The semiconductor device of claim 14, further comprising:

a first transistor and a second transistor on both sides of the first element isolation layer on the first semiconductor layer; and

a third transistor on the second semiconductor layer.

16. The semiconductor device of claim 15, further comprising:

a third element isolation layer in the fourth semiconductor layer, and a fourth transistor on the second semiconductor layer,

wherein the third transistor is on one side of the third element isolation layer, and the fourth transistor is on the other side of the third element isolation layer.

17. The semiconductor device of claim 14, further comprising:

a first well contact on the first semiconductor layer exposed by the third semiconductor layer and the buried insulation layer.

18. The semiconductor device of claim 17, further comprising:

a second well contact on the second semiconductor layer exposed by the fourth semiconductor layer and the second buried insulation layer.

19-24. -24. (canceled)

25. A semiconductor device comprising:

a substrate;

a first impurity region of a first conductivity type on the substrate;

a second impurity region of a second conductivity type on the substrate to be adjacent to the first impurity region;

a first semiconductor layer of the second conductivity type on the first impurity region;

a second semiconductor layer of the first conductivity type on the second impurity region;

a first buried insulation layer on the first semiconductor layer;

a second buried insulation layer on the second semiconductor layer;

a third semiconductor layer on the first buried insulation layer;

a fourth semiconductor layer on the second buried insulation layer;

a first transistor on the first semiconductor layer;

a second transistor on the second semiconductor layer;

a first element isolation layer which separates the first transistor and the second transistor;

a second element isolation layer in the third semiconductor layer shallower than the first element isolation layer; and

a first well contact connected to the first semiconductor layer, the first well contact not between the first transistor and the first element isolation layer.

26. The semiconductor device of claim 25, further comprising:

a third transistor on the first semiconductor layer and separated by the first transistor and the second element isolation layer.

27. (canceled)

28. (canceled)