SELF ALIGNED VIA AND PILLAR CUT FOR AT LEAST A SELF ALIGNED DOUBLE PITCH

• US 20190318960A1
• Filed: 06/25/2019
• Published: 10/17/2019
• Est. Priority Date: 06/30/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Briggs, Benjamin D., Clevenger, Lawrence A., Rizzolo, Michael, Spooner, Terry A., Standaert, Theodorus E.
• Granted Patent: US 10,957,581 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/0335 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5329 Insulating materials

Abstract

A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.

Claims

1. A method of forming via openings comprising:

forming a first set of spacers on sidewalls of a first set of mandrels, the first set of mandrels present on a material layer for forming a second mandrel that is present overlying at least one interlevel dielectric layer;

etching the mandrel material layer using the first set of spacers as an etch mask to form a second set of mandrels, wherein etching the mandrel material layer includes removing the first set of mandrels;

forming a second set of spacers on the second set of mandrels;

etching the hardmask layer using the second set of spacers on the second set of mandrels to define a first pillar of hardmask material;

etching the interlevel dielectric layer using the first pillar of hardmask material and a first via etch mask to provide a first via opening;

depositing a first fill dielectric in the first via opening;

planarizing to remove the first set of spacers;

removing said second set of mandrels with an etch process; and

forming a second via opening in the interlevel dielectric layer.

2. The method of claim 1, wherein said forming the second via opening comprises:

forming a pillar etch mask having an opening exposing a portion of the hardmask layer and the second set of spacers;

etching the portion of the hardmask layer exposed by the pillar etch mask to form a second pillar of hardmask material;

forming a second via mask having an opening exposing a portion of the at least one interlevel dielectric layer through an opening through the hardmask layer that is adjacent to the second pillar of hardmask material; and

etching the second via opening into the at least one interlevel dielectric.

3. The method of claim 1, further comprising filling the first via opening with an electrically conductive material.

4. The method of claim 1, wherein the hardmask layer comprises silicon nitride.

5. The method of claim 1, wherein the hardmask layer comprises a metal nitride selected from the group consisting of tantalum nitride (TaN), tungsten nitride (WN), aluminum nitride (AlN) and combinations thereof.

6. The method of claim 1, further comprising filling the second via opening with an electrically conductive material.

7. The method of claim 1, wherein the interlevel dielectric layer comprises silicon oxide, silicon nitride, SiCOH, organosilicate glass (OSG), fluorine doped silicon dioxide, carbon doped silicon dioxide, porous silicon dioxide, porous carbon doped silicon dioxide, spin-on organic polymeric dielectrics, spin-on silicone based polymeric dielectric, undoped silica glass, diamond like carbon (DLC), methylsilsesquioxane (MSQ) or combinations thereof.

8. The method of claim 1, wherein said etching the interlevel dielectric layer using the first pillar of the hardmask material and the first via etch mask to provide the first via opening comprises anisotropic etch process.

9. The method of claim 1, wherein the second set of mandrels comprises an oxide, nitride, oxynitride or combination thereof.

10. The method of claim 1, wherein the second set of mandrels comprises silicon nitride.

11. The method of claim 1, wherein the interlevel dielectric layer is overlying a device layer.

12. The method of claim 11, wherein the device layer comprises field effect transistors.

13. The method of claim 11, wherein the device layer comprises memory devices.

14. A method of forming via openings comprising:

forming a first set of spacers on sidewalls of a first set of mandrels, the first set of mandrels present on a material layer for forming a second mandrel that is present overlying at least one interlevel dielectric layer;

etching the mandrel material layer using the first set of spacers as an etch mask to form a second set of mandrels, wherein etching the mandrel material layer includes removing the first set of mandrels;

forming a second set of spacers on the second set of mandrels;

etching the hardmask layer using the second set of spacers on the second set of mandrels to define a first pillar of hardmask material;

etching the interlevel dielectric layer using the first pillar of hardmask material and a first via etch mask to provide a first via opening;

removing the second set of mandrels;

forming a pillar etch mask having an opening exposing a portion of the hardmask layer and the second set of spacers;

etching the portion of the hardmask layer exposed by the pillar etch mask to form a second pillar of hardmask material;

forming a second via mask having an opening exposing a portion of the at least one interlevel dielectric layer through an opening through the hardmask layer that is adjacent to the second pillar of hardmask material; and

etching second via opening into the at least one interlevel dielectric.

15. The method of claim 14, wherein removing the second set of mandrels comprises:

depositing a first fill dielectric in the first via opening;

planarizing to remove the first set of spacers; and

said removing said second set of mandrels with an etch process.

16. The method of claim 14, further comprising filling the first via opening and the second via opening with an electrically conductive material.

17. The method of claim 14, wherein the interlevel dielectric layer comprises silicon oxide, silicon nitride, SiCOH, organosilicate glass (OSG), fluorine doped silicon dioxide, carbon doped silicon dioxide, porous silicon dioxide, porous carbon doped silicon dioxide, spin-on organic polymeric dielectrics, spin-on silicone based polymeric dielectric, undoped silica glass, diamond like carbon (DLC), methylsilsesquioxane (MSQ) or combinations thereof.

18. The method of claim 14, wherein said etching the interlevel dielectric layer using the first pillar of the hardmask material and the first via etch mask to provide the first via opening comprises anisotropic etch process.

19. The method of claim 14, wherein the interlevel dielectric layer is overlying a device layer.

20. The method of claim 14, wherein the device layer comprises field effect transistors.