HIGH THRESHOLD VOLTAGE FET WITH THE SAME FIN HEIGHT AS REGULAR THRESHOLD VOLTAGE VERTICAL FET

• US 20190318963A1
• Filed: 04/12/2018
• Published: 10/17/2019
• Est. Priority Date: 04/12/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: MIAO, Xin, CHENG, Kangguo, ZHANG, Chen, XU, Wenyu
• Granted Patent: US 10,490,453 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/311 Etching the insulating layers by chemical or physical means H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/3213 Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A technique relates to a semiconductor device. A first vertical fin is formed with a first gate stack and a second vertical fin with a second gate stack. The second vertical fin has a hardmask on top. The first vertical fin is adjacent to a first bottom source or drain (S/D) region and the second vertical fin is adjacent to a second bottom S/D region. The first gate stack is reduced to a first gate length and the second gate stack to a second gate length, the second gate length being greater than the first gate length because of the hardmask. The hardmask is removed. A first top S/D region is adjacent to the first vertical fin and a second top S/D region is adjacent to the second vertical fin.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a first vertical fin with a first gate stack and a second vertical fin with a second gate stack, wherein the second vertical fin has a hardmask on top, and wherein the first vertical fin is adjacent to a first bottom source or drain (S/D) region and the second vertical fin is adjacent to a second bottom S/D region;

reducing the first gate stack to a first gate length and the second gate stack to a second gate length, the second gate length being greater than the first gate length because of the hardmask;

removing the hardmask; and

forming a first top S/D region adjacent to the first vertical fin and a second top S/D region adjacent to the second vertical fin.

2. The method of claim 1 further comprising forming a first top spacer on the first gate stack and the second gate stack.

3. The method of claim 1 further comprising doping a first upper portion of the first vertical fin and a second upper portion of the second vertical fin subsequent to forming a first top spacer on the first and second gate stacks.

4. The method of claim 3, wherein the first top S/D region is epitaxially grown from the first upper portion and the second top S/D region is epitaxially grown from the second upper portion.

5. The method of claim 3 further comprising forming a second top spacer on the first top spacer.

6. The method of claim 5, wherein the first and second upper portions extend above the first and second top spacers.

7. The method of claim 1, wherein the first vertical fin and the second vertical fin are substantially a same fin length.

8. The method of claim 1, wherein the first gate stack and the second gate stack comprise a high-k dielectric material and at least one gate metal.

9. The method of claim 1 further comprising forming a first vertical transistor and a second vertical transistor;

wherein the first vertical transistor includes the first vertical fin and the first gate stack and the second vertical transistor includes the second vertical fin and the second gate stack.

10. The method of claim 9, wherein the second vertical transistor has a higher threshold voltage than the first vertical transistor defined by the second gate length being greater than the first gate length.

11. The method of claim 9, wherein the second gate length being greater than the first gate length results in the second vertical transistor having a lower leakage current than the first vertical transistor.

12. A semiconductor device comprising:

a first vertical fin with a first gate stack and a second vertical fin with a second gate stack, wherein the first vertical fin and the second vertical fin are substantially a same fin length, wherein the first gate stack has a first gate length and the second gate stack has a second gate length, the second gate length being greater than the first gate length;

a bi-layer top spacer formed on top of the first and second gate stacks;

a first bottom S/D directly on sides of the first vertical fin and a second bottom S/D region directly on sides of the second vertical fin; and

a first top S/D region adjacent to the first vertical fin and a second top S/D region adjacent to the second vertical fin.

13. The semiconductor device of claim 12, wherein the bi-layer top spacer comprises a first top spacer and a second top spacer formed on the first top spacer.

14. The semiconductor device of claim 13, wherein the first and second top spacers comprise different materials.

15. The semiconductor device of claim 12, wherein a first epitaxial cap is on top of the first top S/D region and a second epitaxial cap is on top of the second top S/D region.

16. The semiconductor device of claim 15, wherein the first and second epitaxial caps are different lengths.

17. The semiconductor device of claim 12, wherein top surfaces of the first top S/D region and the second top S/D region are at different heights.

18. The semiconductor device of claim 12, wherein a first vertical transistor includes the first vertical fin and the first gate stack and a second vertical transistor includes the second vertical fin and the second gate stack.

19. The semiconductor device of claim 18, wherein the second gate length being greater than the first gate length results in the second vertical transistor having a lower leakage current than the first vertical transistor.

20. A method of forming a semiconductor device, the method comprising:

forming a first vertical fin with a first gate stack and a second vertical fin with a second gate stack, wherein the first vertical fin and the second vertical fin are substantially a same fin length, wherein the first gate stack has a first gate length and the second gate stack has a second gate length, the second gate length being greater than the first gate length;

forming a bi-layer top spacer on top of the first and second gate stacks;

forming a first bottom S/D region directly on sides of the first vertical fin and a second bottom S/D region directly on sides of the second vertical fin; and

forming a first top S/D region adjacent to the first vertical fin and a second top S/D region adjacent to the second vertical fin.