METHOD OF ADJUSTING SIGNAL TO NOISE RATIO OF SRAM AND INVERTOR STRUCTURE

• US 20190318964A1
• Filed: 03/10/2019
• Published: 10/17/2019
• Est. Priority Date: 04/13/2018
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lee, Wei-Chi, Wang, Han-Tsun, Chen, Chang-Hung, Yang, Po-Yu, Fan, Mei-Ying, Tsai, Mu-Kai, Lin, Guan-Shyan, Kuo, Tsz-Hui, Chen, Cheng-Hsiung
• Granted Patent: US 10,504,788 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. Agate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.

Claims

1. A method of adjusting a signal-to-noise ratio (SNR) of a static random access memory (SRAM), comprising:

providing a substrate, a first long fin structure and a second long fin structure disposed on the substrate, a first short fin structure and a second short fin structure disposed on the substrate and between the first long fin structure and the second long fin structure, a first gate line crossing the first long fin structure, the first short fin structure, and the second long fin structure, and a second gate line crossing the first long fin structure, the second short fin structure and the second long fin structure, wherein the first long fin structure comprises a first side and a second side, the second side faces the first short fin structure, the first side is opposite to the second side, the second long fin structure comprises a third side and the fourth side, the fourth side faces the second short fin structure, and the third side is opposite to the fourth side; and

performing a gate line cutting step, comprising;

removing the second gate line between the first long fin structure and the second short fin structure by a first length;

removing the first gate line between the second long fin structure and the first short fin structure by the first length;

removing the first gate line at the first side of the first long fin structure by a second length; and

removing the second gate line at the third side of the second long fin structure by the second length;

wherein an SNR of an SRAM having the first length greater than the second length is greater than an SNR of an SRAM having the first length equal to the second length.

2. The method of adjusting an SNR of an SRAM of claim 1, wherein the first long fin structure, the second long fin structure, the first short fin structure and the second short fin structure are parallel, the first gate line is parallel to the second gate line, and the first gate line is perpendicular to the first long fin structure.

3. The method of adjusting an SNR of an SRAM of claim 1, wherein when performing the gate line cutting step, the second gate line which is removed by the first length is closer to the first long fin structure and farther from the second short fin structure, the first gate line which is removed by the first length is closer to the second long fin structure and farther from the first short fin structure.

4. The method of adjusting an SNR of an SRAM of claim 3, wherein the first short fin structure does not overlap the second gate line, and the second short fin structure does not overlap the first gate line.

5. The method of adjusting an SNR of an SRAM of claim 1, further comprising:

after performing the gate line cutting step, dividing the first gate line into three first gate line segments, and dividing the second gate line into three second gate line segments; and

forming a dielectric layer to encapsulate an end of each of the three first gate line segments, and an end of each of the three second gate line segments.

6. The method of adjusting an SNR of an SRAM of claim 5, wherein an overlapped region of the first long fin structure and one of the first gate line segments forms a first pull-down transistor, an overlapped region of the first long fin structure and one of the second gate line segments forms a first pass gate transistor, an overlapped region of the first short fin structure and one of the first gate line segments forms a first pull-up transistor, an overlapped region of the second short fin structure and one of the second gate line segments forms a second pull-up transistor, an overlapped region of the second long fin structure and one of the first gate line segments forms a second pass gate transistor, and an overlapped region of the second long fin structure and one of the second gate line segments forms a second pull-down transistor.

7. The method of adjusting an SNR of an SRAM of claim 6, wherein the first pull-down transistor, the second pull-down transistor, the first pull-up transistor, the second pull-up transistor, the first pass gate transistor and the second pass gate transistor together form the SRAM.

8. The method of adjusting an SNR of an SRAM of claim 1, wherein the first short fin structure is between the first long fin structure and the second short fin structure.

9. The method of adjusting an SNR of an SRAM of claim 1, wherein the steps of removing the second gate line between the first long fin structure and the second short fin structure by the first length, removing the first gate line between the second long fin structure and the first short fin structure by the first length, removing the first gate line at the first side of the first long fin structure by the second length, and removing the second gate line at the third side of the second long fin structure by the second length are performed simultaneously.