Spot-Solderable Leads for Semiconductor Device Packages
1. A semiconductor device comprising:
- at least one semiconductor chip attached to a leadframe, the leadframe made of sheet metal of unencumbered full thickness and including leads of a first subset alternating with leads of an adjacent second subset, the subsets having elongated straight lead portions that are parallel to each other in a planar array;
a package of polymeric compound encapsulating the leadframe, the planar array of the straight lead portions of the first and the second subsets are located at a surface of the package, and un-encapsulated surfaces of the leads are coplanar with the surface of the package; and
a cover layer of insulating material located over portions of the un-encapsulated surfaces of the leads, the covered portions of the leads of the first subset alternating with adjacent un-covered portions of the leads of the second subset, and covered portions of the leads of the second subset alternating with adjacent un-covered portions of the leads of the first subset, the un-covered portions of the leads of the first and second subsets having a metallurgical configuration for solder wetting.
A semiconductor device that has at least one semiconductor chip attached to a leadframe made of sheet metal of unencumbered full thickness. The leadframe has leads of a first subset that alternate with leads of a second subset. The leads of the first and second subsets have elongated straight lead portions that are parallel to each other in a planar array. A cover layer of insulating material is located over portions of un-encapsulated lead surfaces. The portions of the leads of the first and second subsets that don'"'"'t have the cover layer have a metallurgical configuration that creates an affinity for solder wetting.
- 1. A semiconductor device comprising:
at least one semiconductor chip attached to a leadframe, the leadframe made of sheet metal of unencumbered full thickness and including leads of a first subset alternating with leads of an adjacent second subset, the subsets having elongated straight lead portions that are parallel to each other in a planar array; a package of polymeric compound encapsulating the leadframe, the planar array of the straight lead portions of the first and the second subsets are located at a surface of the package, and un-encapsulated surfaces of the leads are coplanar with the surface of the package; and a cover layer of insulating material located over portions of the un-encapsulated surfaces of the leads, the covered portions of the leads of the first subset alternating with adjacent un-covered portions of the leads of the second subset, and covered portions of the leads of the second subset alternating with adjacent un-covered portions of the leads of the first subset, the un-covered portions of the leads of the first and second subsets having a metallurgical configuration for solder wetting.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
- 9. A semiconductor device comprising:
at least one semiconductor chip attached to a leadframe, the leadframe made of sheet metal of unencumbered full thickness and including leads of a first subset alternating with leads of a second subset, the subsets having elongated straight lead portions that are parallel to each other in a planar array; a surface layer having a metallurgical configuration for low surface energy for portions of the un-encapsulated lead surfaces, the low surface energy layer of the leads of the first subset alternate with the low surface energy layer of the leads of the adjacent second subset, the low energy surface layer inhibiting wetting by solder material.
- View Dependent Claims (10, 11, 12, 13, 14)
This application is a divisional of U.S. patent application Ser. No. 15/487,186 filed Apr. 13, 2017 and claims the benefit of and priority under U.S.C. § 119(e) of U.S. Provisional Application 62/385,499 (Texas Instruments docket number TI-76969PS, “Semiconductor Device Package Having Spot-Soldering for Leads of Low Resistance and Narrow Spacing”, filed Sep. 9, 2016), the contents of all are Incorporated by reference in their entirety.
Embodiments of the invention are related in general to the field of semiconductor devices and processes, and more specifically to the structure and the method of making semiconductor device packages.
Electronic products have, at their core, printed circuit boards to assemble and interconnect the needed semiconductor devices, power supplies, passive components, control devices, and display devices. Today, an increasing number of these electronic products, such as those that are used in smartphones, electronic cameras, portable computers, automobiles and airplanes are subject to the market trends of higher speed, lower weight, and shrinking product outlines. Consequently, the size, weight, and space required by the printed circuit boards are important.
In order to shrink board outlines, concerted efforts are expended to shrink the individual parts assembled on a board, such as the packages of semiconductor devices and passive components. In addition, a stacking of integrated circuit chips and passive components is widely practiced.
However, it is becoming more difficult to provide enough thermal conductors to dissipate the heat generated by the high density leads that route signals and conduct high currents. Furthermore, there are conflicting product requirements for the metallic leadframes that are used in semiconductor products. For example, one product requirement aims for a tighter density of signal leads while another product requirement aims for stronger power leads and associated areas for heat dissipation. Fine lines and dense spacing are technically possible with thin reduced-thickness leadframes (so-called half-etched leadframes), but those leadframes may become too fragile to handle.
A product example under market pressure for scaling downward is the popular family of Power Block devices that are power switching devices for converting a first DC voltage to a second DC voltage. Particularly suitable for power delivery requirements, the Power Block 121 has two power MOS field effect transistors (FETs) connected in series and coupled together by a common switch node, as Illustrated in the circuit diagram of
Since metal leads 100 with half-etched portions 100b allow the coverage of the half-etched portions by the Insulating molding compound 190b, it is feasible to achieve narrow lead spacing 195 of the metallic leads as well as narrow pin spacing 196 of the metallic leads. Note that the term “lead spacing” refers to the space between metal leads inside the device package and the term “pin spacing” refers to the space between the exposed lead portions that are often soldered to a board.
A power switching device—or Power Block device—converts a first DC voltage to a second DC voltage. Particularly suitable for power delivery requirements are Power Blocks with two semiconductor chips such as two power MOS field effect transistors (FETs) connected in series and coupled together by a common switch node. In these power devices, the connection from the first (control) FET to a supply voltage VIN, the connection from the control FET to a switch node SW, the connection from the switch node to an output voltage VOUT and to a second (synchronous) FET, and the connection from the synchronous FET to a ground potential (PGND) use metal leads that are able to carry high amounts of current. As another requirement, the leads need to be closely spaced to each other for device miniaturization purposes. Moreover, the leads need to be configured for solder attachment to printed circuit boards.
The market trend for semiconductor devices pushes for ever higher frequencies for DC-DC converters. Since the on-resistance of a converter is a defining factor for frequency, the Applicant recognized that leadframe resistance and copper routing layer resistance can be a significant contributor to the total on-resistance of the device. An approach to lower the on-resistance (and thus increase the device frequency) is to reduce the ohmic resistance of the package leads as well as reduce the lead spacing and pin spacing of the device leads.
The Applicant also realized that the ohmic resistance of the package leads can be reduced by the unencumbered full thickness of the metal lead (i.e. discontinue the usage of half-etched leads). Consequently, the common practice of covering half-etched lead portions with molding compound needs to be abandoned. In addition, the spacing between the leads needs to be reduced as much as possible. This latter requirement can shrink the spacing between the full-thickness leads that are exposed at the package surface to the point that the risk of electrical shorts by solder bridging between adjacent leads exceeds acceptable levels. (Solder bridging is a failure mechanism between two adjacent liquefied solder volumes when the surface wetting advances a connecting link between the solder volumes.)
The Applicant minimized the risk of solder bridging between adjacent full-thickness leads when they discovered a way to render restricted portions of adjacent leads un-wettable by solder (i.e. make the restricted portions un-solderable). In one method explained fully below, a polymer-based material is screen printed or inkjet-printed onto portions of adjacent leads. The material is then cured to create a solder-repelling mask. The solder-repelling mask is configured to separate solderable portions of adjacent leads to a safe distance to prevent solder bridging.
In another method explained fully below, the surfaces of selected lead portions are transformed to a surface energy low enough to become non-wettable by solder (and thus they are solder repellant). Such transformation to a low surface energy can be achieved by oxidizing or carbonizing the metal surface. Alternatively, compounds of metal atoms with carbon, nitrogen, sulfur, or other non-metallic elements can be formed on the surface of the selected lead portions to make them solder repellant. Again, the areas of low surface energy are configured to keep the solderable lead areas at a safe distance to prevent solder bridging.
The same distribution of wettable and non-wettable areas is achieved for leads that start with a non-wettable surface by selective plating on metal lead portions with high surface energy plating.
In yet another method explained fully below, insulator-filled grooves are created across the surface of leads. The insulator-filled groves limit solder spreading across the lead surface. The insulator-filled grooves are selected so that the shortest distance from the solder-allowed area of a first lead to the nearest solder-allowed area of an adjacent second lead is the smallest spacing allowed between pins by applicable device design rules.
The array of straight lead portions of the first and second subsets are located at the package surface.
As can be seen in
The un-covered lead portions of the first and second subsets have a metallurgical configuration creating an affinity for solder wetting. Consequently, layer 260 has a geometry that safely prevents solder wicking by adjacent solder connections. In
In another approach to obtain a suitable configuration of cover layer 260, the boundaries of the lead portions of adjacent first and second sets are considered. Specifically, the lead boundaries are selected so that the shortest distance 296 from the border 233 of an un-encapsulated lead of the first set to the nearest border 243 of an un-encapsulated lead of an adjacent second set is the smallest pin spacing 295 allowed by applicable design rules of the device.
As mentioned previously, the market trend for semiconductor devices is higher frequencies for DC-DC power converters. An approach to increasing the frequency is lowering the on-resistance by reducing the ohmic resistance of the package leads and reducing the lead spacing and pin spacing. It is well known that the total on-resistance Ron of two FETs with drain-to-source on-resistances Ron1 and Ron2 can be made smaller than the smallest on-resistance of each individual transistor when the FETs are electrically connected “in parallel”. For negligible parasitic resistances of the interconnections, Ron is obtained by
For two FETs with equal on-resistance (Ron1=Ron2), the parallel positioning of those transistors reduces the total on-resistance Ron by half: Ron=½ Ron1. Moreover, the on-resistance depends on the chip size of the FET. As an example, for a FET with a chip area of 5 mm2, the on-resistance may be about 2.0 ml. If two of these FETs having equal area are interconnected in parallel, they have a total on-resistance Ran of about 1.0 mΩ when the parasitic resistances of the interconnections can be neglected. Otherwise, the on-resistance can realistically be expected to be about 1.1 mΩ.
An analogous relationship holds for parallel arrangement of on-impedances. When a FET with on-impedance Zon1 is connected in parallel to a FET with on-impedance Zon2, and further the phase difference of the current relative to the voltage is the same in both transistors (φ1=φ2), the total on-impedance Zon is given by
If the phase difference between current and voltage is not the same in both transistors (φ1≠φ2), the following relationship holds:
The reciprocal value 1/Zon of the Impedance for parallel connection Is usually smaller than the sum 1/Zon1+Zon2 of the reciprocal discrete impedances. For individual devices, the effort to create low on-impedance FETs is focused on each and every additional fraction of an ohm. Therefore, even small parasitic impedances have to be counted—especially for the interconnecting leads of an assembly board.
Cover layer 260 is made of insulating material selected from a group Including polymeric-based compounds, polyimide, solder mask, silicon nitride, silicon dioxide, and silicon carbide. Preferably, the selected polymeric-based compounds and polyimides can be printed by inkjet or screen technologies. When the polymeric-based compounds and polyimides are cured and hardened, they can serve as masks that are comparable to the solder mask 281 on PCB 280 shown in
The array of straight lead portions of the first and second subsets are located at the package surface.
The processes to achieve a metallurgical configuration having low surface energy (also referred to as low surface tension) Includes the oxidation of the lead metal surface or any other process of forming metal compounds with carbon, nitrogen, sulfur, or other non-metallic elements. While metallic surfaces typically have surface energies in the order of 800 mN/m, materials such as polymers (for instance polytetrafluoroethylene) and silicone can have surface energies <20 mN/m. This range is close to the regime of liquids, which typically have surface energies between 30 and 80 mN/m and thus can be pulled to spread by the high surface energy of metals when deposited on metal surfaces. If the surface energy of a material is less than or equal to the surface energy of the fluid, the fluid will not wet the material. This feature can thus be used to create patterned barriers for controlling the flow of solder. Even when barriers have little or no physical height, the surface energy barrier will generally contain the reflowing solder within the patterned surface energy boundaries.
Alternatively, an inverse method may achieve similar results. In this inverse method, the exposed leads surfaces are originally oxidized (or they otherwise possess low surface energy) and that makes them unsuitable for soldering. Then, in a process such as plating, a thin film of high surface energy material (such as a metal) is deposited on selected portions of the low surface energy leads. As a result, the plating process renders solderable the plated lead portions having high surface energy plating. As an example, when the leads of a copper leadframe originally have copper oxide surfaces (which are notoriously difficult to solder), a plated and patterned thin film of copper, nickel, palladium, or gold will make the plated lead portions solderable.
For the embodiment shown in
While this invention has been described in reference to Illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. As an example, the invention applies to semiconductor chips including field effect transistors, bipolar transistors, power transistors, and integrated circuits. An another example, the invention applies to chips made of silicon, silicon germanium, gallium arsenide, gallium nitride, of any other Ill-V and II-VI compound used in product manufacturing. It is therefore intended that the appended claims encompass any such modifications or embodiments.