MOUNTING SUBSTRATE WAFER, MULTILAYER CERAMIC SUBSTRATE, MOUNTING SUBSTRATE, CHIP MODULE, AND MOUNTING SUBSTRATE WAFER MANUFACTURING METHOD

• US 20190318988A1
• Filed: 06/26/2019
• Published: 10/17/2019
• Est. Priority Date: 08/26/2013
• Status: Abandoned Application

• Current Assignee: Hitachi Metals (Thailand) Ltd.
• Original Assignee: Hitachi Metals (Thailand) Ltd.
• Inventors: NAGATOMO, Hiroyuki, MASUKAWA, Junichi
• Application Number:
  US16/452,622
• Publication Number:
  US 20190318988A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/81192 wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 23/15 Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/49866 characterised by the materials materials of the substrates H01L23/14, of the lead-frames H01L23/49579

Abstract

A wafer for mounting substrates according to the present disclosure includes a multilayer ceramic substrate including top face electrodes, bottom face electrodes, and internal electrodes providing connection between the top face electrodes and the bottom face electrodes, and a wiring pattern formed on a top face of the multilayer ceramic substrate. The wiring pattern has a minimum line width which is equal to or less than 2 μm and a minimum line space which is equal to or less than 2 μm. When the wafer for mounting substrates is zoned into a plurality of regions by the units of 20 mm×20 mm, at least 50% of the regions satisfy the condition that an SFQR in 20 mm×20 mm evaluation region be equal to or less than 2 μm, at the top face of the multilayer ceramic substrate.

Claims

1. A method of producing a wafer for mounting substrates, comprising:

a step of providing a multilayer ceramic substrate including a top-face ceramic layer located at a top face, a bottom-face ceramic layer located at a bottom face, a plurality of top face electrodes extending through the top-face ceramic layer, a plurality of bottom face electrodes extending through the bottom-face ceramic layer, and an intermediate ceramic layer having a plurality of internal electrodes formed therein, the plurality of internal electrodes being internal to the multilayer ceramic substrate and providing electrical connection between the plurality of top face electrodes and the plurality of bottom face electrodes, wherein an inter-electrode-central distance of the plurality of top face electrodes is smaller than an inter-electrode-central distance of the plurality of bottom face electrodes;

a step of applying a planarization process to at least the top face of the multilayer ceramic substrate so that, when the multilayer ceramic substrate is zoned into a plurality of evaluation regions by the units of 20 mm×

20 mm, SFQR (Site Front Least Squares Ranges) in a 20 mm×

20 mm evaluation region is equal to or less than 2 μ

m in at least 50% of the plurality of evaluation regions; and

a step of forming a wiring pattern on the top face of the multilayer ceramic substrate through photolithography, the wiring pattern having a minimum line width which is equal to or less than 2 μ

m and a minimum line space which is equal to or less than 2 μ

m;

wherein,

the step of providing the multilayer ceramic substrate comprises;

a step of providing a first green sheet to compose the top-face ceramic layer and a second green sheet to compose the bottom-face ceramic layer;

a step of subjecting the first and second green sheets to aging;

a step of, after the aging treatment, forming a plurality of holes defining the plurality of top face electrodes and the plurality of bottom face electrodes in the first and second green sheets;

a step of providing at least one third green sheet to compose at least one ceramic layer located between the top-face ceramic layer and the bottom-face ceramic layer;

a step of forming a plurality of holes defining the plurality of internal electrodes in the third green sheet;

a step of filling the plurality of holes of the first, second, and third green sheets with an electrically conductive material;

a step of stacking and laminating the first, second, and third green sheets to form a laminated ceramic green sheet; and

a step of firing the laminated ceramic green sheet to form a sintered ceramic body, the sintered ceramic body including internal electrodes to connect a top face and a bottom face, top face electrodes, and bottom face electrodes.

2. The method of producing a wafer for mounting substrates of claim 1, wherein before and after the step of firing the laminated ceramic green sheet, the multilayer ceramic substrate contracts by a distance of 1% or less along any in-plane direction.

3. A method of producing a wafer for mounting substrates, comprising:

a step of forming a plurality of electrode vias in a green sheet of a ceramic, and filling the electrode vias with an electrode paste from at least one face of the green sheet, to form a green sheet with electrodes;

a step of stacking and laminating a plurality of said green sheets with electrodes so that the respective electrodes are electrically connected therebetween, thereby forming a laminated ceramic green sheet as an integral piece;

a step of firing the laminated ceramic green sheet to form a sintered ceramic body, the sintered ceramic body including internal electrodes to connect a top face and a bottom face, top face electrodes, and bottom face electrodes;

a step of obtaining a multilayer ceramic substrate by processing at least the top face of the sintered ceramic body, the multilayer ceramic substrate having a top face planarized so that, when zoned into a plurality of evaluation regions by the units of 20 mm×

20 mm, SFQR in a 20 mm×

20 mm evaluation region is equal to or less than 2 μ

m in at least 50% of the plurality of evaluation regions; and

a step of forming a wiring pattern through photolithography using an exposure apparatus, the wiring pattern being electrically connected with the electrodes on at least the top face of the multilayer ceramic substrate.

4. The method of producing a wafer for mounting substrates of claim 3, wherein,

the step of forming the wiring pattern comprises:

a step of forming a dielectric layer at least on the top face, and forming at least one or more throughholes in a portion or portions of the dielectric layer for revealing an electrode or electrodes on the top face;

a step of forming a metal seed layer on the dielectric layer and in the throughhole;

a step of applying a photoresist on the metal seed layer;

a step of subjecting the photoresist to exposure by using an exposure apparatus;

a step of subjecting the photoresist having undergone exposure to development for partially removing the photoresist to obtain a photoresist pattern;

a step of allowing a plating layer to deposit on the metal seed layer, through an electroplating technique, in a place of the photoresist pattern where the photoresist has been partially removed, to obtain a wiring pattern;

a step of removing the photoresist pattern; and

a step of removing the metal seed layer formed in any region other than the place where the plating layer has been allowed to deposit.

5. The method of producing a wafer for mounting substrates of claim 3, wherein,

the step of forming the wiring pattern comprises:

a step of forming a dielectric layer at least on the top face, and forming at least one or more throughholes in a portion or portions of the dielectric layer for revealing an electrode or electrodes on the top face;

a step of applying a photoresist on the dielectric layer and over the throughhole;

a step of subjecting the photoresist to exposure by using an exposure apparatus;

a step of subjecting the photoresist having undergone exposure to development for partially removing the photoresist to obtain a photoresist pattern;

a step of forming a metal layer on the photoresist pattern, dielectric layer, and throughhole by a vacuum film deposition technique; and

a step of removing the photoresist pattern to remove (lift-off) the metal deposited on the photoresist pattern, thereby obtaining a wiring pattern while leaving only the metal deposited on the dielectric layer and the throughhole.

6. The method of producing a wafer for mounting substrates of claim 3, wherein, in the step of obtaining the multilayer ceramic substrate, a top-face ceramic layer and a bottom-face ceramic layer of the sintered ceramic body are subjected to a planarization process, one face at a time.

7. The method of producing a wafer for mounting substrates of claim 3, wherein, in the step of obtaining the multilayer ceramic substrate, a top-face ceramic layer and a bottom-face ceramic layer of the sintered ceramic body are subjected to a planarization process, both faces simultaneously.

8. The method of producing a wafer for mounting substrates of claim 6, wherein the step of obtaining the multilayer ceramic substrate comprises a step of processing at least a top face of the top-face ceramic layer by utilizing CMP (Chemical Mechanical Polishing).

9. A laminated ceramic green sheet, comprising:

a first green sheet having a plurality of holes defining a plurality of top face electrodes in the first green sheets;

a second green sheet having a plurality of holes defining a plurality of bottom face electrodes in the second green sheet;

at least one third green sheet located between the first green sheet and the second green sheet;

the at leases one third green sheet having a plurality of holes defining a plurality of internal electrodes in the third green sheet;

an electrically conductive material filling the plurality of holes of the first, second, and third green sheets;

wherein the first green sheet and/or the second green sheet is thicker than the at leases one third green sheet.