SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME

• US 20190318992A1
• Filed: 04/16/2019
• Published: 10/17/2019
• Est. Priority Date: 04/16/2018
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: CHIANG, Ming-Chung
• Granted Patent: US 10,825,769 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A method for manufacturing a semiconductor device is provided. The method includes providing a substrate having a first region and a second region. The method also includes forming an interconnection structure on the first region and a fuse structure on the second region. The method further includes forming a first conductive pad on the interconnection structure. In addition, the method includes forming a capping layer, an etching stop layer and a dielectric layer to cover the first conductive pad and the fuse structure. The method further includes performing an etching process so that a first opening is formed to expose the conductive pad and a second opening is formed directly above the fuse structure. During the etching process, the first dielectric layer has a first etching rate, and the etching stop layer has a second etching rate that is lower than the first etching rate.

Claims

1. A method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate, wherein the semiconductor substrate has a first region and a second region adjacent to the first region;

forming an interconnection structure on the first region of the semiconductor substrate and a fuse structure on the second region of the semiconductor substrate;

forming a first conductive pad on the interconnection structure, wherein the first conductive pad is electrically connected to the interconnection structure;

forming a capping layer to cover the first conductive pad and the fuse structure;

forming an etching stop layer to cover the capping layer;

forming a first dielectric layer to cover the etching stop layer; and

performing a first etching process to remove the first dielectric layer, the etching stop layer and the capping layer so that a first opening is formed in the first region to expose the first conductive pad and a second opening is formed above the fuse structure, wherein during the first etching process, the first dielectric layer has a first etching rate, and the etching stop layer has a second etching rate that is lower than the first etching rate.

2. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the capping layer comprises silicon oxide, and the etching stop layer comprises silicon nitride or aluminum oxide.

3. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the first etching process comprises a dry etching process.

4. The method for manufacturing a semiconductor device as claimed in claim 3, wherein an etchant of the dry etching process comprises fluorine (F).

5. The method for manufacturing a semiconductor device as claimed in claim 1, further comprising:

performing a second etching process before forming the first dielectric layer to remove the etching stop layer on the first region, and to expose the capping layer on the first region.

6. The method for manufacturing a semiconductor device as claimed in claim 5, wherein the second etching process comprises a wet etching process.

7. The method for manufacturing a semiconductor device as claimed in claim 5, forming a second conductive pad on the first region so that there is a trench formed between the first conductive pad and the second conductive pad, wherein performing the second process comprises removing the etching stop layer in the trench.

8. The method for manufacturing a semiconductor device as claimed in claim 1, further comprising:

forming a second dielectric layer to cover the interconnection structure and the fuse structure before forming the first conductive pad, wherein a portion of the second dielectric layer on the second region is removed during the first etching process.

9. The method for manufacturing a semiconductor device as claimed in claim 1, wherein during the first etching process, the capping layer has a third etching rate that is greater than the second etching rate.

10. The method for manufacturing a semiconductor device as claimed in claim 9, further comprising:

forming a barrier layer on the first conductive pad, wherein the barrier layer has a fourth etching rate that is lower than the third rating rate during the first etching process.

11. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the first dielectric layer has a first thickness, and the etching stop layer has a second thickness that is less than the first thickness.

12. A semiconductor device, comprising:

a semiconductor substrate, wherein the semiconductor substrate has a first region and a second region adjacent to the first region;

an interconnection structure and a fuse structure disposed on the first region and the second region of the semiconductor substrate, respectively;

a first dielectric layer covering the interconnection structure and the fuse structure;

a first conductive pad disposed on the interconnection structure, wherein the first conductive pad is electrically connected to the interconnection structure;

a capping layer disposed on the first region and the second region of the semiconductor substrate, wherein the capping layer covers a sidewall of the first conductive pad;

an etching stop layer disposed on the second region of the semiconductor substrate, wherein the etching stop layer covers the capping layer;

a second dielectric layer disposed on the etching stop layer and the capping layer; and

a first opening disposed on the fuse structure and the second region of the semiconductor substrate, wherein the first opening removes the second dielectric layer, the etching stop layer, the capping layer and a portion of the first dielectric layer.

13. The semiconductor device as claimed in claim 12, wherein the capping layer comprises silicon oxide.

14. The semiconductor device as claimed in claim 12, wherein the etching stop layer comprises nitride or metal oxide.

15. The semiconductor device as claimed in claim 12, wherein the etching stop layer comprises silicon nitride or aluminum oxide.

16. The semiconductor device as claimed in claim 12, further comprising:

a second conductive pad disposed on the first region and the first dielectric layer; and

a trench located between the first conductive pad and the second conductive pad, wherein there is no etching stop layer in the trench.

17. The semiconductor device as claimed in claim 12, wherein the capping layer is in direct contact with the second dielectric layer in the first region, and the etching stop layer is in direct contact with the second dielectric layer in the second region.

18. The semiconductor device as claimed in claim 12, wherein the second dielectric layer comprises silicon oxide.

19. The semiconductor device as claimed in claim 12, wherein the second dielectric layer has a first thickness, and the etching stop layer has a second thickness that is less than the first thickness.

20. The semiconductor device as claimed in claim 12, wherein the etching stop layer has a thickness of 50 nm to 150 nm.