MOUNTING STRUCTURES FOR INTEGRATED DEVICE PACKAGES

• US 20190319011A1
• Filed: 03/27/2019
• Published: 10/17/2019
• Est. Priority Date: 04/12/2018
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Analog Devices Global Unlimited Company (Analog Devices, Inc.)
• Inventors: McGeehan, Rigan, Burke, Cillian, O'Donnell, Alan J.
• Granted Patent: US 11,127,716 B2
• Time in Patent Office: Days
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81B 7/0054 between other parts not provided for in B81B7/0048 - B81B7/0051
• CPC Class Codes: B81C 2203/032 Gluing
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/2612 Auxiliary members for layer connectors, e.g. spacers
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73229 Wire and TAB connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06558 : the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06575 : Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 2225/06579 : TAB carriers; beam leads
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/473 : by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 23/4951 : Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/49513 : having bonding material between chip and die pad
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/50 : Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/065 : ABS
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An integrated device package is disclosed. The package can include a carrier and an integrated device die having a front side and a back side. A mounting structure can serve to mount the back side of the integrated device die to the carrier. The mounting structure can comprise a first layer over the carrier and a second element between the back side of the integrated device die and the first layer. The first layer can comprise a first insulating material that adheres to the carrier, and the second element can comprise a second insulating material.

Claims

1. An integrated device package comprising:

a carrier;

an integrated device die having a front side and a back side; and

a mounting structure that serves to mount the back side of the integrated device die to the carrier, the mounting structure comprising a first adhesive layer over the carrier and a second element between the back side of the integrated device die and the first adhesive layer,

wherein the first adhesive layer comprises a first insulating material that adheres to the carrier,

wherein the second element comprises a second insulating material that electrically separates the integrated device die from an electrical interconnect connected to the carrier.

2. The integrated device package of claim 1, wherein the carrier comprises a second integrated device die.

3. The integrated device package of claim 2, wherein the electrical interconnect comprises a bonding wire, the integrated device package further comprising a package substrate, the second integrated device die wire bonded to the package substrate by the bonding wire, wherein a portion of the bonding wire is disposed between the second element and the second integrated device die, the portion of the bonding wire being embedded within the first layer.

4. The integrated device package of claim 3, wherein the bonding wire does not protrude into the second element, and the second element physically and electrically isolates the bonding wire from the back side of the integrated device die.

7. The integrated device package of claim 1, wherein the carrier comprises a package substrate, the package substrate comprises a leadframe substrate or a laminate substrate.

9. The integrated device package of claim 1, wherein the first layer comprises a die attach film (DAF) or an epoxy paste.

11. The integrated device package of claim 1, wherein the second element comprises a solid coating applied over the back side of the integrated device die.

12. The integrated device package of claim 1, wherein the second element comprises a spacer attached to the first layer.

13. The integrated device package of claim 12, wherein the spacer comprises a pathway to provide at least one of electrical, optical, and fluidic communication between an input terminal and an output terminal of the spacer.

17. The integrated device package of claim 12, wherein a coefficient of thermal expansion (CTE) of the spacer is within at least +/−

90% of one or more of a coefficient of expansion of the integrated device die and a coefficient of thermal expansion of the carrier.

19. The integrated device package of claim 1, wherein the mounting structure comprises a third layer between the back side of the integrated device die and the second element such that the second element is embedded between the first layer and the third layer, the third layer comprising a third insulating material.

20. The integrated device package of claim 1, wherein one or both of the first layer and the second element comprises a polymer.

25. A method of manufacturing the integrated device package of claim 1, the method comprising:

mounting the back side of the integrated device die to the carrier by way of the mounting structure,

wherein the second element comprises a second insulating material that electrically separates the integrated device die from the carrier and/or from an electrical interconnect connected to the carrier.

26. The method of claim 25, wherein the second element comprises a second layer, the method further comprising applying the second layer to the back side of a wafer comprising a plurality of device regions, and, after the applying, dicing the wafer into a plurality of integrated device dies, the plurality of integrated device dies comprising the integrated device die.

28. The method of claim 25, further comprising, before the mounting, applying the first layer to a top surface of the carrier.

5. (canceled)

6. (canceled)

8. (canceled)

10. (canceled)

14. (canceled)

15. (canceled)

16. (canceled)

18. (canceled)

21. (canceled)

22. A multi-layer mounting tape for attaching an integrated device die to a carrier and electrically isolating a back side of the integrated device die from the carrier, the multi-layer mounting tape comprising:

a first layer comprising a first insulating material having a first flowable state and a second hardened state;

a second layer over the first layer, the second layer comprising a second insulating material; and

a third layer over the second layer, such that the second layer is embedded between the first layer and the third layer, the third layer comprising a third insulating material, the third insulating material having a first flowable state and a second hardened state.

23. The multi-layer mounting tape of claim 22, wherein the first and third layers each comprise a die attach film (DAF).

24. (canceled)

27. (canceled)

29. (canceled)

30. An integrated device package comprising:

a carrier;

an integrated device die having a front side and a back side; and

a mounting structure that serves to mount the back side of the integrated device die to the carrier, the mounting structure comprising a first adhesive layer over the carrier and a spacer between the back side of the integrated device die and the first adhesive layer,

wherein the spacer includes a pathway to provide at least one of electrical, optical, and fluidic communication between an input terminal and an output terminal of the spacer.

31. The integrated device package of claim 30, wherein the pathway extends vertically through the spacer to provide communication between the carrier and the integrated device die.

33. The integrated device package of claim 30, further comprises a second spacer over the integrated device die, the second spacer includes a second pathway, the second pathway providing communication between the integrated device die and the outside environs.

32. (canceled)