ESD PROTECTION SILICON CONTROLLED RECTIFIER DEVICE

• US 20190319024A1
• Filed: 04/16/2019
• Published: 10/17/2019
• Est. Priority Date: 04/17/2018
• Status: Active Grant

• Current Assignee: DB HiTek Co., Ltd.
• Original Assignee: DB HiTek Co., Ltd.
• Inventors: Noh, Seok Soon, Jang, Joon Tae, Byeon, Joon Hyeok, Kim, Young Chul
• Granted Patent: US 10,879,231 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/66363 Thyristors
• CPC Class Codes: H01L 29/74 Thyristor-type devices, e.g. having four-zone regenerative action two-terminal thyristors H01L29/87
• CPC Class Codes: H01L 29/7436 Lateral thyristors

Abstract

An ESD protection SCR device includes an epitaxial layer provided on a P-type semiconductor substrate, the epitaxial layer having the P-type conductivity, element isolation layers provided on the epitaxial layer, the element isolation layers dividing the epitaxial layer into an anode region and a cathode region, a first well of an N-type conductivity, provided in a portion of the epitaxial layer corresponding to the anode region, a first impurity region provided on a surface of the first well, the first impurity region being connected to an anode terminal and having a high concentration P-type conductivity, a second well of the P-type conductivity, provided in a portion of the epitaxial layer corresponding to the cathode region, a second impurity region provided on a surface of the second well, the second impurity region being connected to a cathode terminal and having a high concentration N-type conductivity, and a floating well of the N-type conductivity, buried in the epitaxial layer.

Claims

1. An ESD protection SCR device comprising:

an epitaxial layer provided on a semiconductor substrate having a P-type conductivity, the epitaxial layer having the P-type conductivity;

a plurality of element isolation layers provided on the epitaxial layer, the plurality of element isolation layers arranged to divide the epitaxial layer into an anode region and a cathode region;

a first well having an N-type conductivity, the first well provided in a portion of the epitaxial layer corresponding to the anode region;

a first impurity region provided on a surface of the first well, the first impurity region being connected to an anode terminal and having the P-type conductivity at a level higher than semiconductor substrate;

a second well having the P-type conductivity, the second well provided in a portion of the epitaxial layer corresponding to the cathode region;

a second impurity region provided on a surface of the second well, the second impurity region being connected to a cathode terminal and having the N-type conductivity at a level higher than the first well; and

a floating well having the N-type conductivity, buried in the epitaxial layer.

2. The ESD protection SCR device of claim 1, wherein the floating well is disposed below both of the anode region and the cathode region.

3. The ESD protection SCR device of claim 1, wherein the floating well defines at least one opening therethrough.

4. The ESD protection SCR device of claim 1, wherein the second impurity region, the epitaxial layer and the first well define an emitter, a base and a collector, respectively, and the floating well is arranged to increase a resistance of the base and decrease a vertical current which flows along the epitaxial layer when the ESD protection SCR device is powered.

5. The ESD protection SCR device of claim 1, further comprising:

a third impurity region having the N-type conductivity at a concentration higher than the first well, the third impurity region being provided on a surface of the first well so as to surround the first impurity region;

a fourth impurity region having the P-type conductivity at a level higher than the semiconductor substrate, the fourth impurity region being provided on a surface of the second well so as to be spaced apart from the second impurity region and connected to a bulk terminal; and

a fifth impurity region having the P-type conductivity at a level higher than the semiconductor substrate, the fifth impurity region being provided on the surface of the second well so as to surround one side of the second impurity region, adjacent to the anode region.

6. The ESD protection SCR device of claim 5, further comprising a shallow well having the N-type conductivity, the shallow well being positioned in the first well and under the third impurity region.

7. The ESD protection SCR device of claim 1, wherein the first well has a ring structure and surrounds the second well.

8. The ESD protection SCR device of claim 1, further comprising:

a drift ion region of the N-type conductivity, provided at both sides of the first well; and

a gate provided on both a surface of the second well and between the drift ion region and the fifth impurity region and a surface of the element isolation layer, the gate being connected to a gate terminal.

9. The ESD protection SCR device of claim 8, further comprising a P-body region disposed under a portion of the gate and a portion of the fifth impurity region.

10. The ESD protection SCR device of claim 1, wherein the element isolation layer additionally separate the epitaxial layer into a P-sub region, and further comprising:

a third well having the P-type conductivity, the third well being disposed in the epitaxial layer of the P-sub region; and

a sixth impurity region having the P-type conductivity, the sixth impurity region being provided on a surface of the third well and being connected to a P-sub terminal.

11. An ESD protection SCR device comprising:

an epitaxial layer provided on semiconductor substrate having a P-type conductivity, the epitaxial layer having the P-type conductivity;

an element isolation layer provided on the epitaxial layer, the element isolation layer separating the epitaxial layer into an anode region and a cathode region;

a first well having an N-type conductivity and provided in a portion of the epitaxial layer corresponding to the anode region;

a first impurity region provided on a surface of the first well, the first impurity region being connected to an anode terminal and having a P-type conductivity higher than that of the semiconductor substrate;

a second well having the P-type conductivity and provided in a portion of the epitaxial layer corresponding to the cathode region;

a second impurity region provided on a surface of the second well, the second impurity region being connected to a cathode terminal and having the N-type conductivity at a level higher than that of the first well;

a floating well having the N-type conductivity, wherein the floating well is buried in the epitaxial layer; and

a shallow well positioned at a lower portion of the first well and spaced apart from the first impurity region, the shallow well having the N-type conductivity.