INTEGRATED CIRCUIT DEVICE

• US 20190319027A1
• Filed: 10/25/2018
• Published: 10/17/2019
• Est. Priority Date: 04/11/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CHUNG, Jae-yup, KIM, II-ryong, KIM, Ju-youn, KIM, Jin-wook, YEO, Kyoung-hwan, JEONG, Yong-gi
• Granted Patent: US 10,804,264 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 : in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 : with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7846 : the means being located in the lateral device isolation region, e.g. STI
• CPC Class Codes: H03K 19/0948 : using CMOS or complementary insulated gate field-effect transistors

Abstract

An integrated circuit device includes a substrate from which a plurality of fin-type active regions protrude, the plurality of fin-type active regions extending in parallel to one another in a first direction, and a plurality of gate structures and a plurality of fin-isolation insulating portions extending on the substrate in a second direction crossing the first direction and at a constant pitch in the first direction, wherein a pair of fin-isolation insulating portions from among the plurality of fin-isolation insulating portions are between a pair of gate structures from among the plurality of gate structures, and the plurality of fin-type active regions include a plurality of first fin-type regions and a plurality of second fin-type regions.

Claims

1. An integrated circuit device comprising:

a substrate;

a plurality of fin-type active regions protruding from the substrate, the plurality of fin-type active regions extending in parallel to one another in a first direction; and

a plurality of gate structures and a plurality of fin-isolation insulating portions extending on the substrate in a second direction crossing the first direction, the plurality of gate structures and the plurality of fin-isolation insulating portions at a constant pitch in the first direction,

wherein a pair of fin-isolation insulating portions from among the plurality of fin-isolation insulating portions are between a first element of a pair of gate structures and a second element of the pair of gate structures, the pair of gate structures being from among the plurality of gate structures, and

the plurality of fin-type active regions comprise a plurality of first fin-type regions and a plurality of second fin-type regions, wherein a pair of first fin-type regions from among the plurality of first fin-type regions extend in a straight line in the first direction and are spaced apart from each other with the pair of fin-isolation insulating portions therebetween, and one of the plurality of second fin-type regions is between the pair of fin-isolation insulating portions.

2. The integrated circuit device of claim 1, wherein

each of the plurality of fin-isolation insulating portions comprises a lower fin-isolation insulating portion and an upper fin-isolation insulating portion on the lower fin-isolation insulating portion, wherein the lower fin-isolation insulating portion is aligned in a vertical direction with respect to the upper fin-isolation insulating portion , and at least a portion of the lower fin-isolation insulating portion and at least a portion of the upper fin-isolation insulating portion have a different material from each other, and

a width of at least a portion of the upper fin-isolation insulating portion in the first direction is greater than a width of the plurality of gate structures in the first direction.

3. The integrated circuit device of claim 2, wherein a vertical level of each of a lowermost surface and an uppermost surface of the lower fin-isolation insulating portion is lower than a vertical level of each of an uppermost surface of the plurality of fin-type active regions and an uppermost surface of the plurality of gate structures.

4. The integrated circuit device of claim 2, wherein the lower fin-isolation insulating portion comprises,

a core insulating pattern, and

a peripheral insulating pattern covering side surfaces and a bottom surface of the core insulating pattern.

5. The integrated circuit device of claim 4, wherein the core insulating pattern comprises an oxide layer and the peripheral insulating pattern comprises a nitride layer.

6. The integrated circuit device of claim 2, wherein the lower fin-isolation insulating portion comprises a single material.

7. The integrated circuit device of claim 1, further comprising:

a plurality of first insulating spacers covering both side walls of the plurality of gate structures; and

a plurality of second insulating spacers covering both side walls of the plurality of fin-isolation insulating portions,

wherein an uppermost surface of the plurality of second insulating spacers is at a lower vertical level than an uppermost surface of the plurality of first insulating spacers.

8. The integrated circuit device of claim 1, wherein the plurality of gate structures comprise a pair of dummy gate structures extending in a straight line in the second direction with the plurality of fin-isolation insulating portions therebetween.

9. The integrated circuit device of claim 1, wherein an uppermost surface of the plurality of fin-isolation insulating portions is at a higher vertical level than an uppermost surface of the plurality of gate structures.

10. The integrated circuit device of claim 9, further comprising:

a plurality of gate insulating capping layers covering a top surface of the plurality of gate structures,

wherein an uppermost surface of the plurality of gate insulating capping layers and the uppermost surface of the plurality of fin-isolation insulating portions have a same vertical level.

11. The integrated circuit device of claim 1, further comprising:

a plurality of source/drain regions on the plurality of fin-type active regions at both sides of the plurality of gate structures and both sides of the plurality of fin-isolation insulating portions; and

a plurality of contact plugs connected to the plurality of source/drain regions.

12. The integrated circuit device of claim 11, wherein the plurality of contact plugs vertically overlap the plurality of first fin-type regions and do not vertically overlap the plurality of second fin-type regions.

13. An integrated circuit device comprising:

a substrate;

a plurality of fin-type active regions protruding from the substrate, the plurality of fin-type active regions having a first region and a second region, the plurality of fin-type active regions extending in parallel to one another in a first direction; and

a plurality of gate structures and a plurality of fin-isolation insulating portions extending on the substrate in a second direction crossing the first direction, the plurality of gate structures and the plurality of fin-isolation insulating portions at a constant pitch in the first direction,

wherein a pair of fin-isolation insulating portions from among the plurality of fin-isolation insulating portions are between a first element and a second element of a pair of gate structures from among the plurality of gate structures, and

the plurality of fin-isolation insulating portions comprise a first fin-isolation insulating portion in the first region and a second fin-isolation insulating portion in the second region, wherein at least a portion of the first fin-isolation insulating portion has a different material from at least a portion of the second fin-isolation insulating portion.

14. The integrated circuit device of claim 13, wherein

the first fin-isolation insulating portion comprises a first lower fin-isolation insulating portion and a first upper fin-isolation insulating portion on the first lower fin-isolation insulating portion,

the second fin-isolation insulating portion comprises a second lower fin-isolation insulating portion and a second upper fin-isolation insulating portion on the second lower fin-isolation insulating portion,

an uppermost surface of each of the first lower fin-isolation insulating portion and the second lower fin-isolation insulating portion is at a higher vertical level than an uppermost surface of the plurality of fin-type active regions and is at a lower vertical level than the plurality of gate structures,

the first upper fin-isolation insulating portion has the same material as the second upper fin-isolation insulating portion, and

at least a portion of the first lower fin-isolation insulating portion has a different material than at least a portion of the second lower fin-isolation insulating portion.

15. The integrated circuit device of claim 14, wherein

the first lower fin-isolation insulating portion comprises a core insulating pattern and a peripheral insulating pattern covering side surfaces and a bottom surface of the core insulating pattern, the core insulating pattern having a different material from the peripheral insulating pattern, and

the second lower fin-isolation insulating portion consists of a single material.

16. The integrated circuit device of claim 15, wherein the peripheral insulating pattern and the second lower fin-isolation insulating portion include a same material.

17. The integrated circuit device of claim 15, wherein the core insulating pattern and the second lower fin-isolation insulating portion include a same material. .

18. The integrated circuit device of claim 13, further comprising:

a plurality of first insulating spacers covering both side walls of the plurality of gate structures; and

a plurality of second insulating spacers covering both side walls of the plurality of fin-isolation insulating portions,

wherein an uppermost surface of the plurality of second insulating spacers is at a lower vertical level than an uppermost surface of the plurality of first insulating spacers, and

an uppermost surface of the plurality of fin-isolation insulating portions is at a higher vertical level than an uppermost surface of the plurality of gate structures.

19. An integrated circuit device comprising:

a substrate;

a plurality of fin-type active regions protruding from the substrate, the plurality of fin-type active regions having a first region and a second region and extending in parallel to one another in a first direction; and

a plurality of gate structures and a plurality of fin-isolation insulating portions extending on the substrate in a second direction crossing the first direction and at a constant pitch in the first direction,

wherein a pair of fin-isolation insulating portions from among the plurality of fin-isolation insulating portions are between a first element and a second element of a pair of gate structures from among the plurality of gate structures in the first region, and

one fin-isolation insulating portion from among the plurality of fin-isolation insulating portions is between a pair of gate structures from among the plurality of gate structures in the second region.

20. The integrated circuit device of claim 19, wherein

a lowermost surface of the plurality of fin-isolation insulating portions is at a lower vertical level than an uppermost surface of the plurality of fin-type active regions, and

an uppermost surface of the plurality of fin-isolation insulating portions is at a higher vertical level than an uppermost surface of the plurality of gate structures.