MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20190319034A1
• Filed: 04/12/2019
• Published: 10/17/2019
• Est. Priority Date: 04/13/2018
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: LEE, Shu-Ming, OU YANG, Tzu-Ming, CHAN, Meng-Chang
• Granted Patent: US 10,756,099 B2
• Time in Patent Office: Days
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/47 with a floating-gate layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 41/48 with a tunnel dielectric layer also being used as part of the peripheral transistor

Abstract

A memory device and a method for manufacturing the memory device are provided. The memory device includes a substrate, a plurality of first gate structures, a first dielectric layer, a second dielectric layer, a third dielectric layer and a contact plug. The first gate structures are formed on an array region of the substrate. The first dielectric layer is formed on top surfaces and sidewalls of the first gate structures. The second dielectric layer is formed on the first dielectric layer and in direct contact with the first dielectric layer. The second dielectric layer and the first dielectric layer are made of the same material. The third dielectric layer is formed between the first gate structures and defines a plurality of contact holes exposing the substrate. The contact plug fills the contact holes.

Claims

1. A memory device, comprising:

a substrate;

a plurality of first gate structures formed on the substrate;

a first dielectric layer formed on top surfaces and sidewalls of the plurality of first gate structures;

a second dielectric layer formed on the first dielectric layer, wherein the second dielectric layer is in direct contact with the first dielectric layer, and the second dielectric layer and the first dielectric layer are made of the same material;

a third dielectric layer formed on the first dielectric layer which is between the plurality of first gate structures, wherein the third dielectric layer defines a plurality of contact holes exposing the substrate; and

a contact plug filling the plurality of contact holes,

wherein the memory device comprises an array region and a peripheral region, and the plurality of first gate structures are formed in the array region.

2. The memory device as claimed in claim 1, wherein the first dielectric layer and the third dielectric layer are nitrides.

3. The memory device as claimed in claim 1, wherein the first dielectric layer, the second dielectric layer, and the third dielectric layer are made of the same material.

4. The memory device as claimed in claim 1, wherein:

in the array region, a width of the second dielectric layer on the first gate structure is smaller than a width of the first dielectric layer on the first gate structure.

5. The memory device as claimed in claim 4, wherein a total thickness of the first dielectric layer and the second dielectric layer from the top surface of the first gate structure is 50-150 nm.

6. The memory device as claimed in claim 2, further comprising a gap-filling dielectric structure, wherein in the array region, the gap-filling dielectric structure is located only on an outer sidewall of the first dielectric layer on the first gate structure closest to the peripheral region, a top surface of the gap-filling dielectric structure is coplanar with a top surface of the first dielectric layer, and the gap-filling dielectric structure and the first dielectric layer are made of different materials.

7. The memory device as claimed in claim 6, further comprising a second gate structure formed in the peripheral region, wherein the first dielectric layer is also formed on a top surface and sidewalls of the second gate structure, and the gap-filling dielectric structure is located on sidewalls of the first dielectric layer on both sides of the second gate structure.

8. The memory device as claimed in claim 7, wherein the second dielectric layer extends over the gap-filling dielectric structure.

9. The memory device as claimed in claim 7, wherein the gap-filling dielectric structure is an oxide, and a top surface of the second dielectric layer in the array region is coplanar with the top surface of the second dielectric layer in the peripheral region.

10. The memory device as claimed in claim 1, wherein the first dielectric layer has a first thickness T1 from the top surface of the first gate structure, the second dielectric layer has a second thickness T2 from a top surface of the first dielectric layer, and a ratio T1/T2 of the first thickness T1 to the second thickness T2 is 0.1-10.0.

11. The memory device as claimed in claim 1, wherein in the array region, a sidewall of the contact plug is in direct contact with the third dielectric layer.

12. A method for manufacturing a memory device, comprising:

providing a substrate;

forming a plurality of first gate structures on the substrate;

forming a first dielectric layer over the substrate and on top surfaces and sidewalls of the plurality of first gate structures, and the first dielectric layer does not fully fill a trench between the plurality of first gate structures;

forming a gap-filling dielectric structure on the first dielectric layer and filling the trench with the gap-filling dielectric structure, and the gap-filling dielectric structure and the first dielectric layer are made of different materials, wherein forming the gap-filling dielectric structure comprises a planarization step such that a top surface of the gap-filling dielectric structure is coplanar with a top surface of the first dielectric layer;

forming a second dielectric layer on the first dielectric layer and the gap-filling dielectric structure, wherein the second dielectric layer is in direct contact with the first dielectric layer, and the second dielectric layer and the first dielectric layer are made of the same material;

performing a first etching process to remove the second dielectric layer and the gap-filling dielectric structure between the plurality of first gate structures;

forming a third dielectric layer on the first dielectric layer which is between the plurality of first gate structures, wherein the third dielectric layer defines a plurality of contact holes exposing the substrate; and

filling the plurality of contact holes with a conductive material to form a contact plug,

wherein the memory device comprises an array region and a peripheral region, and the plurality of first gate structures are formed in the array region.

13. The method for manufacturing the memory device as claimed in claim 12, further comprising forming a second gate structure in the peripheral region;

wherein forming the first dielectric layer comprises forming the first dielectric layer over a top surface and sidewalls of the second gate structure; and

wherein forming the gap-filling dielectric structure comprises forming the gap-filling dielectric structure on sidewalls of the first dielectric layer on both sides of the second gate structure.

14. The method for manufacturing the memory device as claimed in claim 12, after performing the first etching process, wherein:

in the array region, a width of the second dielectric layer on the first gate structure is smaller than a width of the first dielectric layer on the first gate structure.

15. The method for manufacturing the memory device as claimed in claim 12, further comprising:

forming a self-aligned trench between the plurality of first gate structures by the first etching process;

filling the self-aligned trench with a photoresist material;

patterning the photoresist material to form a plurality of first openings between the plurality of first gate structures;

forming a sacrificial layer and filling the plurality of first openings with the sacrificial layer;

removing a remaining portion of the photoresist material to form a plurality of second openings between the plurality of first gate structures;

filling the plurality of second openings with the third dielectric layer; and

performing a second etching process to remove the sacrificial layer and to form the plurality of contact holes.

16. The method for manufacturing the memory device as claimed in claim 15, before filling photoresist material, further comprising forming a protective liner on the first dielectric layer and the second dielectric layer.

17. The method for manufacturing the memory device as claimed in claim 15, wherein the second etching process is a wet etching process, and a ratio of an etching rate of the sacrificial layer to an etching rate of the first dielectric layer is 50-1000 during the second etching process.

18. The method for manufacturing the memory device as claimed in claim 15, after performing the second etching process, further comprising removing the first dielectric layer on the substrate between the plurality of first gate structures.

19. The method for manufacturing the memory device as claimed in claim 12, further comprising:

forming a self-aligned trench between the plurality of first gate structures by the first etching process;

filling the self-aligned trench with a bottom layer material;

forming a middle layer material on the bottom layer material;

forming a photoresist material on the middle layer material, wherein the bottom layer material, the middle layer material, and the photoresist material form a multilayer structure, and wherein the photoresist material has a flat bottom surface and a flat top surface;

patterning the multilayer structure to form a plurality of first openings between the plurality of first gate structures;

filling the plurality of first openings with a sacrificial layer;

removing a remaining portion of the multilayer structure to form a plurality of second openings between the plurality of first gate structures;

filling the plurality of second openings with the third dielectric layer; and

performing a second etching process to remove the sacrificial layer and to form the plurality of contact holes.