MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

• US 20190319041A1
• Filed: 10/01/2018
• Published: 10/17/2019
• Est. Priority Date: 04/12/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: KWAK, Sang Hyon, LEE, Duk Eui, KIM, Nam Gyu
• Granted Patent: US 10,770,474 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0223 formation by oxidation, e.g. oxidation of the substrate
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A manufacturing method of a semiconductor device includes: forming pillars in a first region of a stack structure in which interlayer insulating layers and sacrificial insulating layers are alternately stacked; forming a slit in a second region of the stack structure; and removing the sacrificial insulating layers in the first region. In the removing of the sacrificial insulating layers in the first region, a portion of each of the sacrificial insulating layers, which is adjacent to the slit, and a portion of each of the sacrificial insulating layers, which is disposed between the pillars, may be removed using different etching materials.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming a stack structure including a first region and a second region by alternately stacking interlayer insulating layers and sacrificial insulating layers on a lower structure;

forming pillars penetrating the first region of the stack structure;

forming a slit penetrating the second region of the stack structure;

forming first openings between the interlayer insulating layers by removing the sacrificial insulating layers remaining between a slit-side pillar adjacent to the slit among the pillars and the slit, using a first etching material introduced through the slit; and

forming second openings between the interlayer insulating layers by removing the sacrificial insulating layers remaining between the pillars, using a second etching material different from the first etching material, which is introduced through the first openings.

2. The method of claim 1, further comprising filling the first and second openings with conductive patterns.

3. The method of claim 1, wherein the first etching material has a first etching selection ratio at which it rapidly etches the sacrificial insulating layers as compared with the interlayer insulating layers, and

the second etching material has a second etching selection ratio at which it rapidly etches the sacrificial insulating layers as compared with the interlayer insulating layers,

wherein the first etching selection ratio is lower than the second etching selection ratio.

4. The method of claim 1, wherein the forming of the first openings is performed through dry etching using the first etching material in a gaseous state, and

the forming of the second openings is performed through wet etching using the second etching material in a soluble state.

5. The method of claim 1, wherein the first etching material includes at least one of a gas in which nitrogen trifluoride (NF₃) and oxygen (O₂) are mixed, a gas in which hydrogen fluoride (HF) and oxygen (O₂) are mixed, and a chlorotrifluoride (CIF₃) gas.

6. The method of claim 1, wherein the second etching material includes a phosphoric acid.

7. The method of claim 1, wherein the width of each of the first openings in the direction in which the interlayer insulating layers and the sacrificial insulating layers are stacked increases when approaching the slit.

8. The method of claim 1, wherein the lower structure includes a semiconductor substrate, a conductive layer or a doped silicon layer.

9. The method of claim 1, further comprising, before the first etching material is introduced, forming a protective layer by oxidizing the lower structure exposed through the slit.

10. The method of claim 1, wherein each of the pillars includes:

a vertical channel extending in the direction in which the interlayer insulating layers and the sacrificial insulating layers are stacked;

a tunnel insulating layer surrounding the vertical channel;

a data storage layer surrounding the tunnel insulating layer; and

a blocking insulating layer surrounding the data storage layer.

11. A method of manufacturing a semiconductor device, the method comprising:

forming a stack structure by alternately stacking interlayer insulating layers and sacrificial insulating layers on a lower structure, the stack structure including first regions spaced apart from one another and a second region disposed between the first regions;

forming holes penetrating each of the first regions of the stack structure;

forming pillars filling in the holes, the pillars being divided into first and second pillar groups by the second region, each of the first and second pillar groups including a center pillar and a slit-side pillar;

forming a slit penetrating the second region to a depth to expose the lower structure;

forming a protective layer on the lower structure which is exposed through the slit;

removing only a portion of each of the sacrificial insulating layers which remains between the slit and the slit-side pillar through a first selective etching process by introducing a first etching material through the slit to form first openings between adjacent interlayer insulating layers;

performing a second etching using a second etching material that is different from the first etching material for removing remaining portions of the sacrificial insulating layers adjacent to the slit which were not removed with the first etching, and the sacrificial insulating layers between the pillars.

12. The method of claim 11, wherein the first etching material includes at least one of a gas in which nitrogen trifluoride (NF₃) and oxygen (O₂) are mixed, a gas in which hydrogen fluoride (HF) and oxygen (O₂) are mixed, and a chlorotrifluoride (CIF₃) gas, and

wherein the second etching material is a solution including a phosphoric acid.

13. The method of claim 11, further comprising filling the first and second openings with conductive patterns.

14. The method of claim 11, wherein the first etching material has a first etching selection ratio at which it rapidly etches the sacrificial insulating layers as compared with the interlayer insulating layers, and

the second etching material has a second etching selection ratio at which it rapidly etches the sacrificial insulating layers as compared with the interlayer insulating layers,

wherein the first etching selection ratio is lower than the second etching selection ratio.

15. The method of claim 11, wherein the forming of the first openings is performed through dry etching using the first etching material in a gaseous state, and

the forming of the second openings is performed through wet etching using the second etching material in a soluble state.

16. The method of claim 11, wherein the width of each of the first openings in the direction in which the interlayer insulating layers and the sacrificial insulating layers are stacked increases in a direction approaching the slit.

17. The method of claim 11, wherein the lower structure includes a semiconductor substrate, a conductive layer or a doped silicon layer.

18. The method of claim 11, wherein the protective layer is formed by oxidizing the lower structure exposed through the slit.

19. The method of claim 11, wherein each of the pillars includes:

a vertical channel extending in the direction in which the interlayer insulating layers and the sacrificial insulating layers are stacked;

a tunnel insulating layer surrounding the vertical channel;

a data storage layer surrounding the tunnel insulating layer; and

a blocking insulating layer surrounding the data storage layer.