Three-dimensional vertical NOR Flash Thin-Film Transistor Strings

• US 20190319044A1
• Filed: 06/20/2019
• Published: 10/17/2019
• Est. Priority Date: 02/02/2018
• Status: Active Grant

• Current Assignee: Sunrise Memory Corporation
• Original Assignee: Sunrise Memory Corporation
• Inventors: Harari, Eli
• Granted Patent: US 10,475,812 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53257 the principal metal being a refractory metal
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region

Abstract

A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

Claims

1. A memory structure, comprising:

a semiconductor substrate having a substantially planar surface and including circuitry formed therein for memory circuit operations;

first and second heavily doped regions each formed above the semiconductor substrate and each extending along a first direction orthogonal to the planar surface of semiconductor substrate;

first and second lightly doped regions spaced apart from each other and each being adjacent both the first and second heavily doped regions;

first, second and third word line conductors that are electrically isolated from each other, wherein (i) each word line conductor extends lengthwise along a second direction substantially parallel to the planar surface, (ii) the first and the second word line conductors are (a) a predetermined distance apart along a third direction substantially orthogonal to both the first and second directions, and (b) provided on a first plane substantially parallel to the planar surface, and (iii) the third word line conductor is provided on a second plane that is substantially parallel to the first plane and separated a second predetermined distance from first plane; and

charge-trapping material provided between each word line conductor and each lightly doped region, forming first, second and third variable-threshold thin-film storage transistors, wherein (i) the first heavily doped region, the second heavily doped region, and the charge-trapping material provide each variable-threshold thin-film storage transistor a drain terminal, a source terminal and a charge-trapping region, respectively;

(ii) the first lightly doped region and the first word line conductor provide a channel region and a gate terminal, respectively, for the first variable-threshold thin-film storage transistor;

(iii) the second lightly doped region and the second word line conductor provide a channel region and a gate terminal, respectively, for the second variable-threshold thin-film storage transistor;

(ii) the first lightly doped region and the third word line conductor provide a channel region and a gate terminal, respectively, for the third variable-threshold thin-film storage transistor.

2. The memory structure of claim 1, further comprising first and second interconnection conductors running lengthwise along the third direction, wherein (i) the first interconnection conductor is connected to the drain terminal of each of the variable-threshold thin-film transistor, and (ii) the second interconnection conductor is connected to the source terminal of each of the variable-threshold thin-film storage transistor.

3. The memory structure of claim 2, wherein (i) the first and second heavily doped regions, the first and second lightly doped regions and the charge-trapping material form a representative one of a plurality active columns that are arranged in a two-dimensional array extending along the second and third dimensions, (ii) the first interconnection conductor is one of a plurality of mutually electrically isolated bit line segments, each bit line segment connecting the drain terminal of a variable-threshold thin-film storage transistor formed in each of a plurality of the active columns along one row of the two-dimensional array.

4. The memory structure of claim 3, further comprising a plurality of regional bit line segments each selectably connecting a selected group of the bit line segments.

5. The memory structure of claim 3, further comprising a plurality of segment-select transistors each selectably connecting a corresponding bit line segment to the circuitry in the semiconductor substrate.

6. The memory structure of claim 5, wherein the circuitry in the semiconductor substrate comprises at least a plurality of sense amplifiers distributed throughout the planar surface of the semiconductor substrate, the sense amplifiers being each connected by a different group of one or more segment-select transistors to corresponding bit line segments.

7. The memory structure of claim 5, wherein the segment-select transistors are formed in the semiconductor substrate.

8. The memory structure of claim 3, wherein (i) the first word line conductor provides gate terminals for variable-threshold thin-film transistors in the active columns on its opposite sides, and wherein the drain terminals provided by adjacent active columns on opposite side of the first word line conductor are connected to different bit line segments.

9. The memory structure of claim 3, wherein the second interconnection conductor is one of a plurality of mutually electrically isolated source line segments, each source line segment connecting the source terminal of a variable-threshold thin-film storage transistor formed in each of a plurality of the active columns along one row of the two-dimensional array.

10. The memory structure of claim 9, further comprising a global source line and a plurality of segment-select transistors, each segment-select transistor connecting a predetermined number of source line segments to the global source line.

11. The memory structure of claim 10, further comprising in each active column a pre-charge transistor for electrically connecting the source terminal of a variable-threshold thin-film storage transistor formed in the active column to the drain terminal of the variable-threshold thin-film storage transistor.

12. The memory structure of claim 11, wherein the source terminals connected by each source line segment provide a capacitance that serves as a virtual voltage source during a read, programming, program-inhibit or erase operation on one or more variable-threshold thin-film storage transistors in the active columns associated with the source line segment.

13. The memory structure of claim 3, further comprising a body bias voltage source in the semiconductor substrate, wherein the lightly doped region of each active column is connected to the body bias voltage source by a conductor above or below the active column.

14. The memory structure of claim 9, further comprising a plurality of charging columns each being associated with one of the source line segments, each charging column having first and second heavily doped regions structurally substantially the same as the first and second heavily doped regions of one of the active columns, wherein each charging column further comprises a plurality of pass transistors each selectably connecting the first and second heavily doped regions of the charging column, wherein at least one of the first and second heavily doped regions of the charging column is connected to the circuitry in the semiconductor substrate.

15. The memory structure of claim 14, wherein each charging column is formed between two neighboring source line segments.

16. The memory structure of claim 14, wherein one or more of the word line conductors activate one or more of the pass transistors in one or more of the charging columns.

17. The memory structure of claim 16, further comprising a global source line that connects one or more of the word line conductors that activate one or more of the pass transistors in the one or more charging columns.

18. The memory structure of claim 16, wherein each charging column is connected to a voltage source in the semiconductor substrate by a segment-select transistor in the semiconductor substrate.

19. The memory structure of claim 18, wherein the voltage source supplies an erase voltage for a source terminal during an erase operation.

20. The memory structure of claim 3, wherein the active columns are isolated from each other by an isolation dielectric material or by an air gap.

21. The memory structure of claim 1, wherein the first and third word line conductors are insulated from each other by an isolation dielectric material or air gap.

22. The memory structure of claim 3, wherein the variable-threshold thin-film transistors associated with each active column are organized in parallel into one or more NOR thin-film transistor strings.

23. The memory structure of claim 1, wherein the first and the third word line conductors form steps of a stair-case structure and wherein the first and the third word line conductors are connected at the stair-case structure by vias to third and fourth interconnection conductors, respectively, the third and the fourth interconnection conductors each extend along the third direction.

24. The memory structure of claim 23, wherein second word line conductor is connected to the fourth interconnection conductor.

25. A memory structure comprising first and second modular memory structures provided one on top of the other, wherein each modular memory structure comprises the memory structure of claim 3.

26. The memory structure of claim 25, wherein the first and second modular memory structures are isolated from each other by a dielectric layer.

27. The memory structure of claim 26, wherein active columns in the first and second modular memory structures are aligned along the first direction and wherein in local source lines of corresponding active columns are connected by vias through the dielectric layer.

28. The memory structure of claim 3, further comprising metallic pylons embedded in either one or both of the first and the second heavily doped regions of one or more active columns,

29. The memory structure of claim 28, wherein the metallic pylons each comprises one or more of titanium nitride, tungsten nitride or tungsten.

30. The memory structure of claim 29, wherein the metallic pylon is formed using an atomic layer deposition technique.

31. The memory structure of claim 1, wherein the first and the second lightly doped regions each comprises a first section and a second section, and wherein the first section provides the channel region of a variable-threshold thin-film storage transistors and wherein the second section has a dopant concentration multiple times that of the first section.